| High-throughput layered decoder implementation for quasi-cyclic LDPC codes K Zhang, X Huang, Z Wang IEEE Journal on Selected Areas in Communications 27 (6), 985-994, 2009 | 182 | 2009 |
| High-speed low-power Viterbi decoder design for TCM decoders J He, H Liu, Z Wang, X Huang, K Zhang IEEE transactions on very large scale integration (vlsi) systems 20 (4), 755-759, 2011 | 78 | 2011 |
| A high-throughput LDPC decoder architecture with rate compatibility K Zhang, X Huang, Z Wang IEEE Transactions on Circuits and Systems I: Regular Papers 58 (4), 839-847, 2010 | 48 | 2010 |
| A dual-rate LDPC decoder for china multimedia mobile broadcasting systems K Zhang, X Huang, Z Wang IEEE Transactions on Consumer Electronics 56 (2), 399-407, 2010 | 18 | 2010 |
| Soft decoder architecture of LT codes K Zhang, X Huang, C Shen 2008 IEEE Workshop on Signal Processing Systems, 210-215, 2008 | 16 | 2008 |
| Complexity and performance tradeoffs of near-optimal detectors for cooperative ISI channels Y Peng, K Zhang, AG Klein, X Huang 2010-MILCOM 2010 MILITARY COMMUNICATIONS CONFERENCE, 1753-1758, 2010 | 11 | 2010 |
| A low-complexity rate-compatible LDPC decoder K Zhang, X Huang 2009 Conference Record of the Forty-Third Asilomar Conference on Signals …, 2009 | 9 | 2009 |
| An area-efficient LDPC decoder architecture and implementation for CMMB systems K Zhang, X Huang, Z Wang 2009 20th IEEE International Conference on Application-specific Systems …, 2009 | 9 | 2009 |
| Design and implementation of a belief propagation detector for sparse channels Y Peng, K Zhang, AG Klein, X Huang ASAP 2011-22nd IEEE International Conference on Application-specific Systems …, 2011 | 6 | 2011 |
| Joint optimization of antenna orientation and spectrum allocation for cognitive radio networks W Guo, X Huang, K Zhang 2009 Conference Record of the Forty-Third Asilomar Conference on Signals …, 2009 | 5 | 2009 |
| Design and implementation of a low-complexity symbol detector for sparse channels Y Peng, X Huang, AG Klein, K Zhang IEEE transactions on very large scale integration (VLSI) systems 21 (8 …, 2012 | 4 | 2012 |
| A high SFDR direct digital synthesizer with frequency error free output K Zhang, X Huang 2008 IEEE International Symposium on Circuits and Systems (ISCAS), 3138-3141, 2008 | 2 | 2008 |
| Improved Digital Calibration Technology in a 12-b, 40-MS/s Pipelined ADC H Jia, G Chen, J Cheng, K Zhang, L Shen 2007 7th International Conference on ASIC, 261-264, 2007 | 1 | 2007 |
| A Sample-and-Hole Circuit for Analysis and Design of a 12bit 100MS/s ADC K ZHANG, G ZHOU, Y LIU, G CHEN, J CHENG Microelectronics & Computer 11, 004, 2007 | | 2007 |
