Design of a digital FM demodulator based on a 2nd order all-digital phase-locked loop JPM Brito, S Bampi Proceedings of the 20th annual conference on Integrated circuits and systems …, 2007 | 31 | 2007 |
A 4-bits trimmed CMOS bandgap reference with an improved matching modeling design JPM Brito, S Bampi, H Klimach 2007 IEEE International Symposium on Circuits and Systems (ISCAS), 1911-1914, 2007 | 24 | 2007 |
A low-power RF/analog front-end architecture for LF passive RFID tags with dynamic power sensing FP Cortes, JPM Brito, R Cantalice, E Ghignatti, A Olmos, F Chavez, ... 2014 IEEE International Conference on RFID (IEEE RFID), 60-66, 2014 | 18 | 2014 |
A DC offset and CMRR analysis in a CMOS 0.35 μm operational transconductance amplifier using Pelgrom's area/accuracy tradeoff JPM Brito, S Bampi Microelectronics Journal 40 (9), 1281-1292, 2009 | 16 | 2009 |
A design methodology for matching improvement in bandgap references JPM Brito, H Klimach, S Bampi 8th International Symposium on Quality Electronic Design (ISQED'07), 586-594, 2007 | 16 | 2007 |
Temperature-compensated reference voltage system with very low power consumption based on an SCM structure with transistors of different threshold voltages FC Porras, A Olmos, JPM Brito US Patent 9,383,760, 2016 | 11 | 2016 |
Low-power/low-voltage analog front-end for LF passive RFID tag systems FP Cortes, G Freitas, HLA Pimentel, JPM Brito, F Chavez 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2013 | 6 | 2013 |
CMOS smart temperature sensors for RFID applications JPM Brito, A Rabaeijs 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2013 | 5 | 2013 |
A power management system architecture for LF passive RFID tags FPŃ Cortes, JPM Brito, E Ghignatti Jr, A Olmos, F Chavez, M Lubaszewski Analog Integrated Circuits and Signal Processing 85 (1), 47-55, 2015 | 4 | 2015 |
A 2-transistor sub-1V low power temperature compensated CMOS voltage reference A Olmos, JPM Brito, FJA Ferreira, F Chavez, MS Lubaszewski Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 1-5, 2014 | 4 | 2014 |
Within-die and die-to-die variability on 65nm CMOS: oscillators experimental results JPM Brito, M Lubaszewski, S Bampi 2015 International Workshop on CMOS Variability (VARI), 27-32, 2015 | 2 | 2015 |
Two transistors voltage-measurement-based test structure for fast MOSFET device mismatch characterization JPM Brito, S Bampi IEEE Transactions on Semiconductor Manufacturing 33 (2), 166-173, 2020 | 1 | 2020 |
Two-transistor Voltage-Measurement-Based Test Structure for Fast Extraction of MOS Mismatch Design Parameters JP Martinez Brito, S Bampi 2019 IEEE 32nd International Conference on Microelectronic Test Structures …, 2019 | 1 | 2019 |
Mosfet stacked-pair test structure for mismatch evaluation by estimating the on-resistance ratio JPM Brito, M Lubaszewski, S Bampi 2015 International Workshop on CMOS Variability (VARI), 33-38, 2015 | 1 | 2015 |
Local Random Variability Characterization Structures for FETs in CMOS 65 nm Test-Chip JP Brito, FC Werle, GR Camaratta, S Bampi VARI 2010 First European Workshop on CMOS Variability. Montpellier France, 2010 | 1 | 2010 |
Análise de projetos de módulos amplificadores e comparadores em tecnologia CMOS 0.35µm– FP Cortes, E Fabris, JPMBS BRITO, S Bampi Instituto de Informática da Universidade Federal do Rio Grande do Sul, Porto …, 2003 | 1 | 2003 |
Local Variability Evaluation on Effective Channel Length Extracted With Shift-and-Ratio Method JPM Brito, S Bampi IEEE Transactions on Electron Devices 67 (11), 4662-4666, 2020 | | 2020 |
EDITAL PERMANENTE DE SELEÇÃO PARA INGRESSO NO CURSO DE DOUTORADO Nº01/2018 JPM BRITO UNIVERSIDADE FEDERAL DO RIO GRANDE DO SUL, 2019 | | 2019 |
Estruturas de Teste para Avaliação de Variabilidade Estatística em Dispositivos CMOS abaixo de 100nm. GR Camaratta, FC Werle, JPM Brito Salão de Iniciação Científica (21.: 2009 out. 19-23: Porto Alegre, RS …, 2009 | | 2009 |
23rd South Symposium on Microelectronics M Johann, A Girardi, JPM Brito | | 2008 |