| Compact model of drain current in short-channel triple-gate FinFETs N Fasarakis, A Tsormpatzoglou, DH Tassis, I Pappas, K Papathanasiou, ... IEEE transactions on electron devices 59 (7), 1891-1898, 2012 | 67 | 2012 |
| Backscattering coefficient and drift-diffusion mobility extraction in short channel MOS devices I Pappas, G Ghibaudo, CA Dimitriadis, C Fenouillet-Béranger Solid-State Electronics 53 (1), 54-56, 2009 | 34 | 2009 |
| Electrical transport characterization of nano CMOS devices with ultra-thin silicon film G Ghibaudo, M Mouis, L Pham-Nguyen, K Bennamane, I Pappas, A Cros, ... 2009 International Workshop on Junction Technology, 58-63, 2009 | 27 | 2009 |
| Compact capacitance model of undoped or lightly doped ultra-scaled triple-gate FinFETs N Fasarakis, A Tsormpatzoglou, DH Tassis, I Pappas, K Papathanasiou, ... IEEE transactions on electron devices 59 (12), 3306-3312, 2012 | 23 | 2012 |
| Display systems with hybrid emitter circuits MA Horowitz, I Pappas, E Buckley, WT Blank US Patent 10,861,380, 2020 | 20 | 2020 |
| A simple and continuous polycrystalline silicon thin-film transistor model for SPICE implementation I Pappas, AT Hatzopoulos, DH Tassis, N Arpatzanis, S Siskos, ... Journal of applied physics 100 (6), 2006 | 19 | 2006 |
| Active-matrix liquid crystal displays-operation, electronics and analog circuits design I Pappas, S Siskos, CA Dimitriadis New Developments in Liquid Crystals 12, 147-170, 2009 | 18 | 2009 |
| A fast and compact analog buffer design for active matrix liquid crystal displays using polysilicon thin-film transistors I Pappas, S Siskos, CA Dimitriadis IEEE Transactions on Circuits and Systems II: Express Briefs 55 (6), 537-540, 2008 | 17 | 2008 |
| A novel FPGA architecture and an integrated framework of CAD tools for implementing applications K Siozios, G Koutroumpezis, K Tatas, N Vassiliadis, V Kalenteridis, ... IEICE transactions on information and systems 88 (7), 1369-1380, 2005 | 16 | 2005 |
| An integrated FPGA design framework: Custom designed FPGA platform and application mapping toolset development V Kalenteridis, H Pournara, K Siozios, K Tatas, G Koytroympezis, ... 18th International Parallel and Distributed Processing Symposium, 2004 …, 2004 | 16 | 2004 |
| Analytical current-voltage model for nanocrystalline silicon thin-film transistors AT Hatzopoulos, I Pappas, DH Tassis, N Arpatzanis, CA Dimitriadis, ... Applied physics letters 89 (19), 2006 | 15 | 2006 |
| Pan-warping and modifying sub-frames with an up-sampled frame rate WA Hunt, WT Blank, I Pappas, M Yee, E Buckley US Patent 11,176,901, 2021 | 14 | 2021 |
| Multi-layer fabrication for pixels with calibration compensation I Pappas US Patent 10,902,769, 2021 | 13 | 2021 |
| Display with redundant light emitting devices I Pappas, S Lord, YH Li US Patent 10,157,573, 2018 | 13 | 2018 |
| Display with cell voltage compensation I Pappas, S Lord, YH Li US Patent 10,283,053, 2019 | 12 | 2019 |
| A new threshold‐voltage compensation technique of poly‐Si TFTs for AMOLED display pixel circuits I Pappas, S Siskos, CA Dimitriadis Journal of the Society for Information Display 18 (10), 721-731, 2010 | 12 | 2010 |
| A complete platform and toolset for system implementation on fine-grain reconfigurable hardware V Kalenteridis, H Pournara, K Siozos, K Tatas, N Vassiliadis, I Pappas, ... Microprocessors and Microsystems 29 (6), 247-259, 2005 | 12 | 2005 |
| Signal adjustment circuit I Pappas, CN Chleirigh US Patent App. 14/563,590, 2016 | 9 | 2016 |
| Feedback circuit for calibrating a current mode display WT Blank, I Pappas US Patent 10,930,188, 2021 | 8 | 2021 |
| A new analog buffer using low-temperature polysilicon thin-film transistors for active-matrix displays I Pappas, S Siskos, CA Dimitriadis IEEE transactions on electron devices 54 (2), 219-224, 2007 | 8 | 2007 |
