| 7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory T Tanaka, M Helm, T Vali, R Ghodsi, K Kawai, JK Park, S Yamada, F Pan, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 142-144, 2016 | 144 | 2016 |
| A 3bit/cell 32Gb NAND flash memory at 34nm with 6MB/s program throughput and with dynamic 2b/cell blocks configuration mode for a program throughput increase up to 13MB/s GG Marotta, A Macerola, A D'Alessandro, A Torsi, C Cerafogli, C Lattaro, ... 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 444-445, 2010 | 58 | 2010 |
| A 128Gb 3b/cell NAND flash design using 20nm planar-cell technology G Naso, L Botticchio, M Castelli, C Cerafogli, M Cichocki, P Conenna, ... 2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013 | 35 | 2013 |
| Chunk definition for partial-page read V Moschiano, L Pilolli US Patent 9,940,193, 2018 | 11 | 2018 |
| Memory device distributed controller system L De Santis, L Pilolli US Patent 7,420,849, 2008 | 10 | 2008 |
| Memory device distributed controller system L De Santis, L Pilolli US Patent 8,116,138, 2012 | 7 | 2012 |
| Data interleaving module L Pilolli, ML Gallese, M Castelli US Patent 8,804,452, 2014 | 5 | 2014 |
| Peak power management in a memory device L Yu, JS Parry, L Pilolli US Patent 11,520,497, 2022 | 4 | 2022 |
| Systems and methods involving memory-side (NAND-side) write training to improve data valid windows AM Maccarrone, L Pilolli, AFZ Ghalam, CY Chen US Patent 10,861,517, 2020 | 3 | 2020 |
| Memory device interface communicating with set of data bursts corresponding to memory dies via dedicated portions for command processing L Pilolli US Patent 11,347,663, 2022 | 2 | 2022 |
| Apparatus and methods for serializing data output L Pilolli, AM Maccarrone, H Choi, Q Tang, AFZ Ghalam US Patent 10,658,041, 2020 | 2 | 2020 |
| Methods for operating a distributed controller system in a memory device L De Santis, L Pilolli US Patent 9,772,779, 2017 | 2 | 2017 |
| Techniques to calibrate an impedance level L Pilolli, AM Maccarrone, J Chen, Q Tang US Patent 11,282,550, 2022 | 1 | 2022 |
| Systems and methods involving write training to improve data valid windows AM Maccarrone, L Pilolli, AFZ Ghalam, CY Chen US Patent 11,211,104, 2021 | 1 | 2021 |
| Level shifter with reduced duty cycle variation AFZ Ghalam, L Pilolli, MG WON US Patent 10,911,033, 2021 | 1 | 2021 |
| Methods and apparatus for providing redundancy in memory V Moschiano, G Santin, ML Gallese, L Pilolli US Patent 10,446,258, 2019 | 1 | 2019 |
| Single node power management for multiple memory devices M Castelli, L De Santis, L Pilolli, ML Gallese US Patent 9,349,423, 2016 | 1 | 2016 |
| Dual data channel peak power management L Nubile, L Pilolli, L Yu, A Mohammadzadeh, W Di Francesco, B Iorio US Patent App. 18/494,841, 2024 | | 2024 |
| Memory dice internal clock L Yu, L Pilolli, B Iorio US Patent 11,960,764, 2024 | | 2024 |
| Memory device interface communicating with set of data bursts corresponding to memory dies via dedicated portions for command processing L Pilolli US Patent 11,934,325, 2024 | | 2024 |
