Longest prefix match lookup using hash function C Basso, JL Calvignac, GT Davis, PC Patel US Patent 7,702,630, 2010 | 249 | 2010 |
Network communications for operating system partitions C Basso, JL Calvignac, CJ Chang, P Damon, RE Fuhs, N Vaidhyanathan, ... US Patent 7,697,536, 2010 | 216 | 2010 |
Network processor interface for building scalable switching systems JJ Allen Jr, BM Bass, JL Calvignac, SP Gaur, MC Heddes, MS Siegel, ... US Patent 6,868,082, 2005 | 184 | 2005 |
Method and system for managing congestion in a network PIA Barri, BM Bass, JL Calvignac, IO Clemminck, MC Heddes, CD Jeffries, ... US Patent 6,657,962, 2003 | 169 | 2003 |
Data structures for efficient processing of multicast transmissions C Basso, JL Calvignac, MC Heddes, JF Logan, FJ Verplanken US Patent 6,836,480, 2004 | 152 | 2004 |
IBM PowerNP network processor: Hardware, software, and applications JR Allen, BM Bass, C Basso, RH Boivie, JL Calvignac, GT Davis, ... IBM Journal of research and development 47 (2.3), 177-193, 2003 | 133 | 2003 |
Network processor, memory organization and methods BM Bass, JL Calvignac, MC Heddes, PC Patel, JG Revilla, MS Siegel, ... US Patent 6,460,120, 2002 | 133 | 2002 |
Chip to chip interface for interconnecting chips JL Calvignac, M Heddes, KC Imming, JF Logan, T Ozguner US Patent 6,910,092, 2005 | 129 | 2005 |
Network processor with single interface supporting tree search engine and CAM JL Calvignac, GT Davis, M Heddes, MS Siegel US Patent 7,167,471, 2007 | 127 | 2007 |
Longest prefix match lookup using hash function C Basso, JL Calvignac, GT Davis, PC Patel US Patent 7,089,240, 2006 | 126 | 2006 |
Data switch J Calvignac, D Orsatti, G Toubol, F Verplanken, C Basso US Patent 6,195,335, 2001 | 124 | 2001 |
Receive queue device with efficient queue flow control, segment placement and virtualization mechanisms W Boyd, J Calvignac, CJ Chang, D Joseph, R Recio US Patent App. 10/235,672, 2004 | 108 | 2004 |
Hop-by-hop flow control in an ATM network C Basso, J Calvignac, D Orsatti, F Verplanken US Patent 5,787,071, 1998 | 108 | 1998 |
Data structures for efficient processing of IP fragmentation and reassembly C Basso, JL Calvignac, MC Heddes, JF Logan, FJ Verplanken US Patent 6,937,606, 2005 | 104 | 2005 |
Method and system for in-site and on-line reprogramming of hardware logics with remote loading in a network device JP Aldebert, C Basso, J Calvignac, P Chemla, D Orsatti, F Verplanken, ... US Patent 5,794,033, 1998 | 103 | 1998 |
Network switch using network processor and methods JJ Allen Jr, BM Bass, JL Calvignac, SP Gaur, MC Heddes, MS Siegel, ... US Patent 6,404,752, 2002 | 102 | 2002 |
Method and system for frame and protocol classification JL Calvignac, GT Davis, AM Gallo, MC Heddes, RB Leavens, MS Siegel US Patent 6,775,284, 2004 | 101 | 2004 |
Checkpointing mechanism for fault-tolerant systems H Alaiwan, J Calvignac, JL Combes, A Pauporte, C Basso, F Kermarec US Patent 5,235,700, 1993 | 100 | 1993 |
Selection of receive-queue based on packet attributes F Abel, C Basso, JL Calvignac, N Vaidhyanathan, FJ Verplanken, ... US Patent 8,675,660, 2014 | 96 | 2014 |
Dynamic fair queuing to support best effort traffic in an ATM network J Calvignac, D Orsatti, F Verplanken US Patent 5,629,928, 1997 | 96 | 1997 |