| Realization of Resource Efficient Block RAM Based Eight Bit Adder in FPGA G Dhanabalan, V Karutharaja, M Sakthimohan 2019 IEEE International Conference on Intelligent Techniques in Control …, 2019 | 19 | 2019 |
| Synchronization of on-chip serial interconnect transceivers using delay locked loop (DLL) V Karutharaja, M Bhaskar, B Venkataramani 2011 International Conference on Signal Processing, Communication, Computing …, 2011 | 5 | 2011 |
| A Comparative Review: Performance Parameters of Fin, Nanowire and Nanosheet Field Effect Transistors on 5nm Node V Karutharaja, NB Balamurugan, M Suguna, DS Kumar 2024 7th International Conference on Devices, Circuits and Systems (ICDCS …, 2024 | | 2024 |
| ZigBee Based Home Automation Using MSP430. A Aravindh, V Chandrasekaran, M Balasubramanian, MV Karutharaja | | 2014 |
| DESIGN OF DRAM BASED FPGA MPG BRUNO, M GOWTHAM, MV KARUTHARAJA | | 2014 |
| Pulse width-Control Circuit Using Programmable Duty Cycle With LUT & Delay Line Technique D Mookambigai, V Karutharaja | | 2013 |
| Oil well Monitoring and Control based on ZIGBEE Wireless Networks A Prabakaran, S Raja, M Vignesh, V Karutharaja | | 2013 |
Dhanabalan GVel Tech Rangarajan Dr. Sagunthala R & D Institute of Science and Technology在 veltech.edu.in 的电子邮件经过验证
