| Device and circuit-level assessment of GaSb/Si heterojunction vertical tunnel-FET for low-power applications MR Tripathy, AK Singh, A Samad, S Chander, K Baral, PK Singh, S Jit IEEE Transactions on Electron Devices 67 (3), 1285-1292, 2020 | 110 | 2020 |
| III-V/Si staggered heterojunction based source-pocket engineered vertical TFETs for low power applications Manas Ranjan Tripathy, Ashish Kumar Singh, Kamalaksha Baral, Prince Kumar ... Superlattices and Microstructures, 2020 | 49 | 2020 |
| Two-dimensional analytical modeling for electrical characteristics of Ge/Si SOI-tunnel FinFETs S.Chander, S.Baishya, S.Kumar, P.K.Singh, K.Baral, M.R.Tripathy, A.K.Singh ... Superlattices and Microstructures 131, 30-39, 2019 | 39 | 2019 |
| TFET on Selective Buried Oxide (SELBOX) Substrate with Improved ION/IOFF Ratio and Reduced Ambipolar Current D Barah, AK Singh, B Bhowmick Silicon 11 (2), 973-981, 2019 | 35 | 2019 |
| Simulation study and comparative analysis of some TFET structures with a novel partial-ground-plane (PGP) based TFET on SELBOX structure AK Singh, MR Tripathy, S Chander, K Baral, PK Singh, S Jit Silicon 12 (10), 2345-2354, 2020 | 30 | 2020 |
| Investigation of DC, RF and linearity performances of a back-gated (BG) heterojunction (HJ) TFET-on-selbox-substrate (STFET): Introduction to a BG-HJ-STEFT based CMOS inverter AK Singh, MR Tripathy, K Baral, PK Singh, S Jit Microelectronics journal 102, 104775, 2020 | 27 | 2020 |
| Impact of heterogeneous gate dielectric on DC, RF and circuit-level performance of source-pocket engineered Ge/Si heterojunction vertical TFET M. R. Tripathy, A. K. Singh, et al Semicond. Sci. Technol., 2020 | 26 | 2020 |
| Impact of interface trap charges on device level performances of a lateral/vertical gate stacked Ge/Si TFET-on-SELBOX-substrate Ashish Kumar Singh, Manas Ranjan Tripathy, Kamalaksha Baral, Prince Kumar ... Applied Physics A 126, 2020 | 21 | 2020 |
| Impact of interface trap charges on electrical performance characteristics of a source pocket engineered Ge/Si heterojunction vertical TFET with HfO2/Al2O3 laterally stacked … MR Tripathy, A Samad, AK Singh, PK Singh, K Baral, AK Mishra, S Jit Microelectronics Reliability 119, 114073, 2021 | 20 | 2021 |
| Source pocket engineered underlap stacked-oxide cylindrical gate tunnel FETs with improved performance: design and analysis PK Singh, K Baral, S Kumar, S Chander, MR Tripathy, AK Singh, S Jit Applied Physics A 126 (3), 1-11, 2020 | 17 | 2020 |
| GaSb/GaAs Type-II Heterojunction TFET on SELBOX Substrate for Dielectric Modulated Label-Free Biosensing Application AK Singh, MR Tripathy, K Baral, S Jit IEEE Transactions on Electron Devices 69 (9), 5185-5192, 2022 | 15 | 2022 |
| Deep insight into DC/RF and linearity parameters of a novel back gated ferroelectric TFET on SELBOX substrate for ultra low power applications AK Singh, MR Tripathy, PK Singh, K Baral, S Chander, S Jit Silicon 13 (11), 3853-3863, 2021 | 13 | 2021 |
| 2-D analytical modeling of drain and gate-leakage currents of cylindrical gate asymmetric halo doped dual material-junctionless accumulation mode MOSFET K Baral, PK Singh, S Kumar, A Singh, M Tripathy, S Chander, S Jit AEU-International Journal of Electronics and Communications 116, 153071, 2020 | 12 | 2020 |
| Performance comparison of Ge/Si hetero-junction vertical tunnel FET with and without gate-drain underlapped structure with application to digital inverter MR Tripathy, AK Singh, A Samad, K Baral, PK Singh, S Jit 2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-4, 2020 | 10 | 2020 |
| Device-Level Performance Comparison of Some Pocket Engineered III-V/Si Hetero-Junction Vertical Tunnel Field Effect Transistor Manas Ranjan Tripathy, Ashish Kumar Singh, Sweta Chander, Prince Kumar Singh ... 5th International Conference on Devices, Circuits and Systems (ICDCS),, 180-183, 2020 | 8 | 2020 |
| Analytical Drain Current Model for Source Pocket Engineered Stacked Oxide SiO2/HfO2 Cylindrical Gate TFETs PK Singh, K Baral, S Kumar, MR Tripathy, AK Singh, RK Upadhyay, ... Silicon 13 (6), 1731-1739, 2021 | 7 | 2021 |
| Ferroelectric gate heterojunction TFET on selective buried oxide (SELBOX) substrate for distortionless and low power applications AK Singh, MR Tripathy, K Baral, PK Singh, S Jit 2020 4th IEEE electron devices technology & manufacturing conference (EDTM), 1-4, 2020 | 7 | 2020 |
| Design and Performance Assessment of HfO2/SiO2 Gate Stacked Ge/Si Heterojunction TFET on SELBOX Substrate (GSHJ-STFET) AK Singh, MR Tripathy, K Baral, S Jit Silicon 14 (17), 11847-11858, 2022 | 6 | 2022 |
| Device and circuit-level performance comparison of vertically grown all-Si and Ge/Si hetero-junction TFET MR Tripathy, A Samad, AK Singh, PK Singh, K Baral, S Jit 2020 IEEE International Conference on Electronics, Computing and …, 2020 | 6 | 2020 |
| Impact of Gate Dielectrics on Analog/RF Performance of Double Gate Tunnel Field Effect Transistor PK Singh, K Baral, S Chandler, Sanjay Kumar, M R Tripathy, A K Singh, S Jit 3rd International Conference on Electronics, Materials Engineering & Nano …, 2019 | 6 | 2019 |
Satyabrata JitIndian Institute of Technology (Banaras Hindu University) Varanasi, India在 iitbhu.ac.in 的电子邮件经过验证
