| 15.5 A 28nm 64Kb 6T SRAM computing-in-memory macro with 8b MAC operation for AI edge chips X Si, YN Tu, WH Huang, JW Su, PJ Lu, JH Wang, TW Liu, SY Wu, R Liu, ... 2020 IEEE international solid-state circuits conference-(ISSCC), 246-248, 2020 | 201 | 2020 |
| 15.2 A 28nm 64Kb inference-training two-way transpose multibit 6T SRAM compute-in-memory macro for AI edge chips JW Su, X Si, YC Chou, TW Chang, WH Huang, YN Tu, R Liu, PJ Lu, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 240-242, 2020 | 167 | 2020 |
| 16.3 A 28nm 384kb 6T-SRAM computation-in-memory macro with 8b precision for AI edge chips JW Su, YC Chou, R Liu, TW Liu, PJ Lu, PC Wu, YL Chung, LY Hung, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 250-252, 2021 | 150 | 2021 |
| 14.3 A 65nm computing-in-memory-based CNN processor with 2.9-to-35.8 TOPS/W system energy efficiency using dynamic-sparsity performance-scaling architecture and energy … J Yue, Z Yuan, X Feng, Y He, Z Zhang, X Si, R Liu, MF Chang, X Li, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 234-236, 2020 | 135 | 2020 |
| A local computing cell and 6T SRAM-based computing-in-memory macro with 8-b MAC operation for edge AI chips X Si, YN Tu, WH Huang, JW Su, PJ Lu, JH Wang, TW Liu, SY Wu, R Liu, ... IEEE Journal of Solid-State Circuits 56 (9), 2817-2831, 2021 | 80 | 2021 |
| A 4-Kb 1-to-8-bit configurable 6T SRAM-based computation-in-memory unit-macro for CNN-based AI edge processors YC Chiu, Z Zhang, JJ Chen, X Si, R Liu, YN Tu, JW Su, WH Huang, ... IEEE Journal of Solid-State Circuits 55 (10), 2790-2801, 2020 | 78 | 2020 |
| STICKER-IM: A 65 nm computing-in-memory NN processor using block-wise sparsity optimization and inter/intra-macro data reuse J Yue, Y Liu, Z Yuan, X Feng, Y He, W Sun, Z Zhang, X Si, R Liu, Z Wang, ... IEEE Journal of Solid-State Circuits 57 (8), 2560-2573, 2022 | 34 | 2022 |
| A two-way SRAM array based accelerator for deep neural network on-chip training H Jiang, S Huang, X Peng, JW Su, YC Chou, WH Huang, TW Liu, R Liu, ... 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 34 | 2020 |
| Two-way transpose multibit 6T SRAM computing-in-memory macro for inference-training AI edge chips JW Su, X Si, YC Chou, TW Chang, WH Huang, YN Tu, R Liu, PJ Lu, ... IEEE Journal of Solid-State Circuits 57 (2), 609-624, 2021 | 33 | 2021 |
| A 8-b-precision 6T SRAM computing-in-memory macro using segmented-bitline charge-sharing scheme for AI edge chips JW Su, YC Chou, R Liu, TW Liu, PJ Lu, PC Wu, YL Chung, LY Hong, ... IEEE Journal of Solid-State Circuits 58 (3), 877-892, 2022 | 28 | 2022 |
| A 6.54-to-26.03 TOPS/W computing-in-memory RNN processor using input similarity optimization and attention-based context-breaking with output speculation R Guo, H Li, R Liu, Z Zhang, L Tang, H Sun, L Liu, MF Chang, S Wei, ... 2021 Symposium on VLSI Technology, 1-2, 2021 | 8 | 2021 |
| 15.2 a 28nm 64Kb inference-training two-way transpose multibit 6T SRAM compute-in-memory macro for AI edge chips, in 2020 IEEE international solid-state circuits conference-(ISSCC) JW Su, X Si, YC Chou, TW Chang, WH Huang, YN Tu, R Liu, PJ Lu, ... IEEE, Piscataway, 2020 | 6 | 2020 |
Meng-Fan ChangNational Tsing Hua University, Taiwan在 ee.nthu.edu.tw 的电子邮件经过验证
Meng-Fan ChangNational Tsing Hua University, Taiwan在 ee.nthu.edu.tw 的电子邮件经过验证
Xin SiSoutheast University在 seu.edu.cn 的电子邮件经过验证