Raccoon: Closing digital {Side-Channels} through obfuscated execution A Rane, C Lin, M Tiwari 24th USENIX Security Symposium (USENIX Security 15), 431-446, 2015 | 319 | 2015 |
Vale: Verifying {High-Performance} Cryptographic Assembly Code B Bond, C Hawblitzel, M Kapritsos, KRM Leino, JR Lorch, B Parno, ... 26th USENIX security symposium (USENIX security 17), 917-934, 2017 | 183 | 2017 |
Everest: Towards a verified, drop-in replacement of HTTPS K Bhargavan, B Bond, A Delignat-Lavaud, C Fournet, C Hawblitzel, ... 2nd Summit on Advances in Programming Languages, 2017 | 92 | 2017 |
Secure, Precise, and Fast Floating-Point Operations on x86 Processors A Rane, C Lin, M Tiwari USENIX Security Symposium, 2016 | 43 | 2016 |
Microstache: A lightweight execution context for in-process safe region isolation L Mogosanu, A Rane, N Dautenhahn Research in Attacks, Intrusions, and Defenses: 21st International Symposium …, 2018 | 34 | 2018 |
Enhancing performance optimization of multicore chips and multichip nodes with data structure metrics A Rane, J Browne Proceedings of the 21st international conference on Parallel architectures …, 2012 | 32 | 2012 |
Autoscope: Automatic suggestions for code optimizations using perfexpert OA Sopeju, M Burtscher, A Rane, J Browne Proceedings of the International Conference on Parallel and Distributed …, 2011 | 27 | 2011 |
Experiences in tuning performance of hybrid MPI/OpenMP applications on quad-core systems A Rane, D Stanzione Proc. of 10th LCI Int’l Conference on High-Performance Clustered Computing, 2009 | 27 | 2009 |
Enhancing performance optimization of multicore/multichip nodes with data structure metrics A Rane, J Browne ACM Transactions on Parallel Computing (TOPC) 1 (1), 1-20, 2014 | 13 | 2014 |
Performance optimization of data structures using memory access characterization A Rane, J Browne 2011 IEEE International Conference on Cluster Computing, 570-574, 2011 | 13 | 2011 |
Unification of Static and Dynamic Analyses to Enable Vectorization A Rane, R Krishnaiyer, CJ Newburn, J Browne, L Fialho, Z Matveev 27th International Workshop on Languages and Compilers for Parallel Computing, 2014 | 6 | 2014 |
Poster: determining code segments that can benefit from execution on GPUs A Rane, S Sardeshpande, J Browne Proceedings of the 2011 Companion on High Performance Computing Networking …, 2011 | 4 | 2011 |
PerfExpert and MACPO: Which code segments should (not) be ported to MIC? A Rane, J Browne, L Koesterke TACC-Intel High Performance Computing Symposium, 2012 | 3* | 2012 |
A systematic process for efficient execution on Intel's heterogeneous computation nodes A Rane, J Browne, L Koesterke Proceedings of the 1st Conference of the Extreme Science and Engineering …, 2012 | 1 | 2012 |
A Study of the Hybrid Programming Paradigm on Multicore Architectures A Rane Arizona State University, 2009 | 1 | 2009 |
Broad-Based Side-Channel Defenses for Modern Microprocessors A Rane The University of Texas at Austin, 2019 | | 2019 |