| DESIGN OF HIGH EFFICIENCY TWO STAGE POWER AMPLIFIER IN 0.13 UM RF CMOS TECHNOLOGY FOR 2.4 GHZ WLAN APPLICATION. SR Sahu, AY Deshmukh International Journal of VLSI Design & Communication Systems 4 (4), 2013 | 15 | 2013 |
| Review of Junctionless transistor using CMOS technology and MOSFETs SR Sahu, RS Agrawal, SM Balwani Int. J. Comput. Appl 2012, 8-11, 2012 | 13 | 2012 |
| Finger Motion Controlled Biomedical Wheelchair S Pawar, S Pandey, S Kedar, M Jadhav, S Sahu 5th IEEE International Conference on Advances in Science and Technology …, 2023 | 2 | 2023 |
| Eye Controlled Wheelchair Using Raspberry Pi R Gupta, R Kori, S Hambir, A Upadhayay, S Sahu Available at SSRN 3586951, 2020 | 2 | 2020 |
| Computation and Analysis of Excitatory Synapse and Integrate & Fire Neuron: 180nm MOSFET and CNFET Technology SSR Sushma Srivastava, Shridhar Sahu IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) 8 (1), 60-72, 2018 | 2* | 2018 |
| Vedic Multiplier Using Carry look ahead adder J Suryawanshi, D Gawade, N Tank, S Worlikar, S Sahu 5th IEEE International Conference on Advances in Science and Technology …, 2023 | 1 | 2023 |
| A 10 dBm-25 dBm, 0.363 mm^ sup 2^ TWO STAGE 130 nm RF CMOS POWER AMPLIFIER SR Sahu, AY Deshmukh International Journal of VLSI design & Communication systems 4 (5), 107, 2013 | 1 | 2013 |
| Error Analysis of Sine-Cosine Computation using CORDIC Algorithm A Nandoskar, N Parihar, S Gupta, S Yadav, S Sahu Recent Advances in Electrical & Electronic Engineering 16 (4), 2023 | | 2023 |
Dr. Rahul AgrawalAssistant Professor,G H Raisoni College of Engineering,Nagpur在 raisoni.net 的电子邮件经过验证
