| A 1.2 V 20 nm 307 GB/s HBM DRAM with at-speed wafer-level IO test scheme and adaptive refresh considering temperature distribution K Sohn, WJ Yun, R Oh, CS Oh, SY Seo, MS Park, DH Shin, WC Jung, ... IEEE Journal of Solid-State Circuits 52 (1), 250-260, 2016 | 104 | 2016 |
| A 10b 320 MS/s 40 mW open-loop interpolated pipeline ADC M Miyahara, H Lee, D Paik, A Matsuzawa 2011 Symposium on VLSI Circuits-Digest of Technical Papers, 126-127, 2011 | 29 | 2011 |
| Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM) H Lee, S Kang, HS Yu, WJ Yun, JH Jung, S Ahn, WS Kim, B Kil, YC Sung, ... 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 169-172, 2016 | 6 | 2016 |
| A 6 bit, 7 mW, 700 MS/s subranging ADC using CDAC and gate-weighted interpolation H Lee, Y Asada, M Miyahara, A Matsuzawa IEICE Transactions on Fundamentals of Electronics, Communications and …, 2013 | 6 | 2013 |
| A 6-bit subranging ADC with single CDAC interpolation H Lee, M Miyahara, A Matsuzawa 2013 IEEE International Conference of Electron Devices and Solid-state …, 2013 | 3 | 2013 |
| Design of interpolated pipeline ADC using low-gain open-loop amplifiers H Lee, M Miyahara, A Matsuzawa IEICE transactions on electronics 96 (6), 838-849, 2013 | 3 | 2013 |
| A 12-bit interpolated pipeline ADC using body voltage controlled amplifier H Lee, M Miyahara, A Matsuzawa IEICE Transactions on Fundamentals of Electronics, Communications and …, 2013 | 1 | 2013 |
