| Channel geometry impact and narrow sheet effect of stacked nanosheet CW Yeung, J Zhang, R Chao, O Kwon, R Vega, G Tsutsui, X Miao, ... 2018 IEEE international electron devices meeting (IEDM), 28.6. 1-28.6. 4, 2018 | 81 | 2018 |
| Extremely scaled gate-first high-k/metal gate stack with EOT of 0.55 nm using novel interfacial layer scavenging techniques for 22nm technology node and beyond K Choi, H Jagannathan, C Choi, L Edge, T Ando, M Frank, P Jamison, ... 2009 Symposium on VLSI Technology, 138-139, 2009 | 79* | 2009 |
| Sub-25nm FinFET with advanced fin formation and short channel effect engineering T Yamashita, VS Basker, T Standaert, CC Yeh, T Yamamoto, K Maitra, ... 2011 Symposium on VLSI Technology-Digest of Technical Papers, 14-15, 2011 | 76 | 2011 |
| Ultrafast measurements and physical modeling of NBTI stress and recovery in RMG FinFETs under diverse DC–AC experimental conditions N Parihar, U Sharma, RG Southwick, M Wang, JH Stathis, S Mahapatra IEEE Transactions on Electron Devices 65 (1), 23-30, 2017 | 70 | 2017 |
| FINFET technology featuring high mobility SiGe channel for 10nm and beyond D Guo, G Karve, G Tsutsui, KY Lim, R Robison, T Hook, R Vega, D Liu, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 66 | 2016 |
| High-k metal gate fundamental learning and multi-Vt options for stacked nanosheet gate-all-around transistor J Zhang, T Ando, CW Yeung, M Wang, O Kwon, R Galatage, R Chao, ... 2017 IEEE International Electron Devices Meeting (IEDM), 22.1. 1-22.1. 4, 2017 | 62 | 2017 |
| Special reliability features for Hf-based high-/spl kappa/gate dielectrics TP Ma, HM Bu, XW Wang, LY Song, W He, M Wang, HH Tseng, PJ Tobin IEEE Transactions on Device and Materials Reliability 5 (1), 36-44, 2005 | 60 | 2005 |
| Modeling of NBTI kinetics in RMG Si and SiGe FinFETs, part-I: DC stress and recovery N Parihar, RG Southwick, M Wang, JH Stathis, S Mahapatra IEEE Transactions on Electron Devices 65 (5), 1699-1706, 2018 | 50 | 2018 |
| Electrical properties and interfacial structure of epitaxial LaAlO3 on Si (001) JW Reiner, A Posadas, M Wang, M Sidorov, Z Krivokapic, FJ Walker, ... Journal of Applied Physics 105 (12), 2009 | 49 | 2009 |
| ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell K Cheng, A Khakifirooz, P Kulkarni, S Ponoth, B Haran, A Kumar, T Adam, ... 2011 Symposium on VLSI Technology-Digest of Technical Papers, 128-129, 2011 | 46 | 2011 |
| Reliability challenges for the 10nm node and beyond JH Stathis, M Wang, RG Southwick, EY Wu, BP Linder, EG Liniger, ... 2014 IEEE International Electron Devices Meeting, 20.6. 1-20.6. 4, 2014 | 45 | 2014 |
| Stacked Gate-All-Around Nanosheet pFET with Highly Compressive Strained Si1-xGex Channel S Mochizuki, M Bhuiyan, H Zhou, J Zhang, E Stuckert, J Li, K Zhao, ... 2020 IEEE International Electron Devices Meeting (IEDM), 2.3. 1-2.3. 4, 2020 | 40 | 2020 |
| FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node Q Liu, B DeSalvo, P Morin, N Loubet, S Pilorget, F Chafik, S Maitrejean, ... 2014 IEEE International Electron Devices Meeting, 9.1. 1-9.1. 4, 2014 | 38 | 2014 |
| Reliability of advanced high-k/metal-gate n-FET devices JH Stathis, M Wang, K Zhao Microelectronics Reliability 50 (9-11), 1199-1202, 2010 | 38 | 2010 |
| Electron tunneling spectroscopy study of traps in high-k gate dielectrics: Determination of physical locations and energy levels of traps M Wang, W He, TP Ma Applied Physics Letters 86 (19), 2005 | 32 | 2005 |
| Superior PBTI reliability for SOI FinFET technologies and its physical understanding M Wang, R Muralidhar, JH Stathis, BP Linder, H Jagannathan, ... IEEE electron device letters 34 (7), 837-839, 2013 | 31 | 2013 |
| Multiple-Vt solutions in nanosheet technology for high performance and low power applications R Bao, K Watanabe, J Zhang, J Guo, H Zhou, A Gaul, M Sankarapandian, ... 2019 IEEE International Electron Devices Meeting (IEDM), 11.2. 1-11.2. 4, 2019 | 30 | 2019 |
| Observer-Based H ∞ Synchronization and Unknown Input Recovery for a Class of Digital Nonlinear Systems W Zhang, H Su, F Zhu, M Wang Circuits, Systems, and Signal Processing 32, 2867-2881, 2013 | 30 | 2013 |
| Modeling of NBTI kinetics in replacement metal gate Si and SiGe FinFETs—Part-II: AC stress and recovery N Parihar, RG Southwick, M Wang, JH Stathis, S Mahapatra IEEE Transactions on Electron Devices 65 (5), 1707-1713, 2018 | 28 | 2018 |
| Growth and structural properties of crystalline LaAlO3 on Si (0 0 1) JW Reiner, A Posadas, M Wang, TP Ma, CH Ahn Microelectronic engineering 85 (1), 36-38, 2008 | 25 | 2008 |
