关注
Marco Procaccini
Marco Procaccini
Technology Researcher - National Research Council - CNR, Italy
在 cnr.it 的电子邮件经过验证
标题
引用次数
引用次数
年份
Axiom: A scalable, efficient and reconfigurable embedded platform
R Giorgi, M Procaccini, F Khalili
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 480-485, 2019
312019
A design space exploration tool set for future 1k-core high-performance computers
R Giorgi, M Procaccini, F Khalili
Proceedings of the Rapid Simulation and Performance Evaluation: Methods and …, 2019
152019
The AXIOM project: IoT on heterogeneous embedded platforms
A Filgueras, M Vidal, M Mateu, D Jiménez-González, C Alvarez, ...
IEEE Design & Test 38 (5), 74-81, 2019
142019
Analyzing the impact of operating system activity of different linux distributions in a distributed environment
R Giorgi, M Procaccini, F Khalili
2019 27th Euromicro International Conference on Parallel, Distributed and …, 2019
112019
Energy efficiency exploration on the zynq ultrascale+
R Giorgi, F Khalili, M Procaccini
2018 30th International Conference on Microelectronics (ICM), 48-54, 2018
112018
Translating timing into an architecture: the synergy of COTSon and HLS (domain expertise—designing a computer architecture via HLS)
R Giorgi, F Khalili, M Procaccini
International Journal of Reconfigurable Computing 2019, 1-18, 2019
72019
Bridging a data-flow execution model to a lightweight programming model
R Giorgi, M Procaccini
2019 International Conference on High Performance Computing & Simulation …, 2019
72019
Reconfigurable Logic Interface Architecture for CPU-FPGA Accelerators
F Khalili, R Giorgi, M Procaccini
Acaces 2018 Postser Abstract, 13-16, 2018
62018
Distributed large-scale graph processing on FPGAs
A Sahebi, M Barbone, M Procaccini, W Luk, G Gaydadjiev, R Giorgi
Journal of big Data 10 (1), 95, 2023
52023
An fpga-based scalable hardware scheduler for data-flow models
M Procaccini, F Khalili, R Giorgi
Acaces Poster Abstract 2018, 9-12, 2018
32018
DRT: a lightweight runtime for developing benchmarks for a dataflow execution model
R Giorgi, M Procaccini, A Sahebi
Architecture of Computing Systems: 34th International Conference, ARCS 2021 …, 2021
22021
A data-flow execution engine for scalable embedded computing
M Procaccini, R Giorgi
Acaces Poster Abstract 2017, 91-94, 2017
22017
HashGrid: An optimized architecture for accelerating graph computing on FPGAs
A Sahebi, M Procaccini, R Giorgi
Future Generation Computer Systems 162, 107497, 2025
12025
Accelerating Large-Scale Graph Processing with FPGAs: Lesson Learned and Future Directions
M Procaccini, A Sahebi, M Barbone, W Luk, G Gaydadjiev, R Giorgi
15th Workshop on Parallel Programming and Run-Time Management Techniques for …, 2024
12024
X86_64 vs aarch64 performance validation with cotson
R Giorgi, M Procaccini
Acaces 2019 Postser Abstract, 261-264, 2019
12019
An FPGA-based Scalable Hardware Scheduler for Data-Flow Models
R Giorgi, M Procaccini, F Khalili
Proceedings of International workshop on FPGAS for Domain Experts (FPODE …, 2018
12018
A survey of graph convolutional networks (GCNs) in FPGA-based accelerators
M Procaccini, A Sahebi, R Giorgi
Journal of Big Data 11 (1), 163, 2024
2024
An Extended Tracing System for the COTSon Simulator
M Procaccini, R Giorgi
Acaces 2020 Poster Abstracts, 1-4, 2020
2020
From COTSon to HLS: translating timing into an architecture
R Giorgi, F Khalili, M Procaccini
International workshop on FPGAS for Domain Experts, 2018
2018
FPGAs (ReConFig18) Additional Reviewers
A Sanaullah, A Rodriguez, A Engel, A Otero, B Green, D Danopoulos, ...
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