| Vertical access device and apparatuses having a body connection line, and related method of operating the same KM Karda, RN Gupta, S Pulugurtha, CV Mouli, W Mueller US Patent 8,878,271, 2014 | 59 | 2014 |
| Apparatuses having memory cells with two transistors and one capacitor, and having body regions of the transistors coupled with reference voltages KM Karda, C Mouli, S Pulugurtha, RN Gupta US Patent 10,607,988, 2020 | 46 | 2020 |
| Organic FETs with HWCVD silicon nitride as a passivation layer and gate dielectric SP Tiwari, P Srinivas, S Shriram, NS Kale, SG Mhaisalkar, VR Rao Thin Solid Films 516 (5), 770-772, 2008 | 35 | 2008 |
| New AAT for 4F2 DRAM with a body contact US Patent 9,773,888, 2017 | 32* | 2017 |
| Apparatuses having a vertical memory cell KM Karda, RN Gupta, S Pulugurtha, CV Mouli, W Mueller US Patent 9,577,092, 2017 | 22 | 2017 |
| Apparatuses having memory cells with two transistors and one capacitor, and having body regions of the transistors coupled with reference voltages KM Karda, C Mouli, S Pulugurtha, RN Gupta US Patent 10,381,357, 2019 | 17 | 2019 |
| Memory devices including memory cells and related methods G Huang, H Liu, CV Mouli, S Pulugurtha US Patent 10,608,012, 2020 | 11 | 2020 |
| Semiconductor devices including vertical memory cells and methods of forming same W Mueller, SD Tang, S Dhir, S Pulugurtha US Patent 9,373,715, 2016 | 11 | 2016 |
| Passing access line structure in a memory device US Patent 9,761,590, 2017 | 8* | 2017 |
| Integrated assemblies having shield lines between digit lines, and methods of forming integrated assemblies SD Tang, S Pulugurtha, RJ Hill, Y Gao, NR Tapias, Y Litao, H Liu US Patent 11,069,687, 2021 | 5 | 2021 |
| Underbody contact to horizontal access device for vertical three-dimensional (3D) memory US Patent App. 16/943,163, 2020 | 5* | 2020 |
| Memory device having 2-transistor vertical memory cell US Patent App. 16/722,813, 2019 | 5* | 2019 |
| Patterned gate OFETs with inorganic High-K gate dielectric materials for all P-type Organic circuits SP Tiwari, D Maji, P Srinivas, NS Kale, VR Rao European Materials Research Society (EMRS) Spring Meeting, 2007 | 4 | 2007 |
| Metal insulator semiconductor (MIS) contact in three dimensional (3D) vertical memory KM Karda, DC Pandey, Y Litao, S Pulugurtha, Y Gao, H Liu US Patent 11,538,809, 2022 | 3 | 2022 |
| Recessed Access Device and DRAM Constructions US Patent App. 15/898,086, 2018 | 3* | 2018 |
| Integrated assemblies having conductive material along three of four sides around active regions and methods of forming integrated assemblies US Patent App. 16/868,133, 2020 | 2* | 2020 |
| D. maji, Ramesh RN, HN Raval, Srinivas P., V. Ramgopal Rao,“Low Voltage Organic circuits with Polythiophene semiconductor and High-K Gate dielectric”, 10th Int. Conf SP Tiwari Advanced Materials (ICAM), 2007 | 2 | 2007 |
| Field effect transistors with gate fins and method of making the same S Pulugurtha, Y Zhang, J Alsmeier, M Togo US Patent App. 17/562,635, 2023 | 1 | 2023 |
| Integrated assemblies, and methods of forming integrated assemblies Y Litao, S Pulugurtha, H Liu US Patent 11,563,010, 2023 | 1 | 2023 |
| Memory device including calibration operation and transistor having adjustable threshold voltage AJ Kanago, J Guha, S Pulugurtha, S Sugiura US Patent App. 17/215,904, 2022 | 1 | 2022 |
Shree Prakash TiwariProfessor, Department of Electrical Engineering, Indian Institute of Technology Jodhpur在 iitj.ac.in 的电子邮件经过验证
Shree Prakash TiwariProfessor, Department of Electrical Engineering, Indian Institute of Technology Jodhpur在 iitj.ac.in 的电子邮件经过验证