| Using predictivemodeling for cross-program design space exploration in multicore systems S Khan, P Xekalakis, J Cavazos, M Cintra 16th International Conference on Parallel Architecture and Compilation …, 2007 | 94 | 2007 |
| Eliminating redundant fragment shader executions on a mobile gpu via hardware memoization JM Arnau, JM Parcerisa, P Xekalakis ACM SIGARCH Computer Architecture News 42 (3), 529-540, 2014 | 77 | 2014 |
| Combining thread level speculation helper threads and runahead execution P Xekalakis, N Ioannou, M Cintra Proceedings of the 23rd international conference on Supercomputing, 410-420, 2009 | 54 | 2009 |
| Teapot: A toolset for evaluating performance, power and image quality on mobile graphics systems JM Arnau, JM Parcerisa, P Xekalakis Proceedings of the 27th international ACM conference on International …, 2013 | 52 | 2013 |
| Apparatus and method for efficiently implementing a processor pipeline PP Lai, E Schuchman, D Keppel, DM Khartikov, P Xekalakis, JB Fryman, ... US Patent 10,409,763, 2019 | 50 | 2019 |
| Boosting mobile GPU performance with a decoupled access/execute fragment processor JM Arnau, JM Parcerisa, P Xekalakis ACM SIGARCH Computer Architecture News 40 (3), 84-93, 2012 | 50 | 2012 |
| Parallel frame rendering: Trading responsiveness for energy on a mobile gpu JM Arnau, JM Parcerisa, P Xekalakis Proceedings of the 22nd international conference on Parallel architectures …, 2013 | 40 | 2013 |
| Applying decay to reduce dynamic power in set-associative caches G Keramidas, P Xekalakis, S Kaxiras High Performance Embedded Architectures and Compilers: Second International …, 2007 | 34 | 2007 |
| 4t-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors S Kaxiras, P Xekalakis Proceedings of the 2004 international symposium on Low power electronics and …, 2004 | 32 | 2004 |
| Hardware apparatuses and methods to fuse instructions PP Lai, TN Sondag, S Winkel, P Xekalakis, E Schuchman, J Iyer US Patent 10,324,724, 2019 | 28 | 2019 |
| Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code region R Martinez, EG Codina, P Lopez, MT Lapuerta, P Xekalakis, G Tournavitis, ... US Patent 10,013,326, 2018 | 25 | 2018 |
| Ascib: Adaptive selection of cache indexing bits for removing conflict misses A Ros, P Xekalakis, M Cintra, ME Acacio, JM García Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012 | 24 | 2012 |
| Toward a more accurate understanding of the limits of the TLS execution paradigm N Ioannou, J Singer, S Khan, P Xekalakis, P Yiapanis, A Pocock, G Brown, ... IEEE International Symposium on Workload Characterization (IISWC'10), 1-12, 2010 | 24 | 2010 |
| Effective processor verification with logic fuzzer enhanced co-simulation N Kabylkas, T Thorn, S Srinath, P Xekalakis, J Renau MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021 | 18 | 2021 |
| A simple mechanism to adapt leakage-control policies to temperature S Kaxiras, P Xekalakis, G Keramidas Proceedings of the 2005 international symposium on Low power electronics and …, 2005 | 18 | 2005 |
| Method and apparatus for controlling a mxcsr G Magklis, JM Codina, CB Zilles, M Neilly, S Samudrala, AM Vicente, ... US Patent App. 13/995,416, 2013 | 16 | 2013 |
| Method and apparatus for implementing a dynamic out-of-order processor pipeline DM Khartikov, N Neelakantam, JH Kelm, P Xekalakis US Patent 9,612,840, 2017 | 15 | 2017 |
| Method and apparatus for implementing and maintaining a stack of predicate values with stack synchronization instructions in an out of order hardware software co-designed processor JD Collins, J Iyer, S Winkel, P Xekalakis, HH Chen, R Brauch US Patent App. 14/576,915, 2016 | 12 | 2016 |
| Instruction and logic to perform a fused single cycle increment-compare-jump PP Lai, TN Sondag, S Winkel, P Xekalakis, E Schuchman US Patent App. 14/582,053, 2016 | 11 | 2016 |
| Branch Predictor with Jump Ahead Logic to Jump Over Portions of Program Code Lacking Branches P Xekalakis, P Marcuello, F Latorre US Patent App. 13/150,970, 2012 | 11 | 2012 |
Marcelo CintraHead of Scientific Computing at CAESAR and Honorary Professor at University of Edinburgh在 caesar.de 的电子邮件经过验证
