| Design of low-area and high speed pipelined single precision floating point multiplier T Krishnan, S Saravanan 2020 6th International conference on advanced computing and communication …, 2020 | 10 | 2020 |
| Design and implementation of modified BCD digit multiplier for digit-by-digit decimal multiplier P Anguraj, T Krishnan Analog Integrated Circuits and Signal Processing 107, 683-694, 2021 | 8 | 2021 |
| Design of high-speed RCA based 2-D bypassing multiplier for fir filter T Krishnan, S Saravanan, AS Pillai, P Anguraj Materials Today: Proceedings 33, 3692-3696, 2020 | 7 | 2020 |
| Design of an Area-Efficient Various N-point Support radix-2/22 FFT using Modified Butterfly Units Parthibaraj Anguraj, Thiruvenkadam Krishnan,Kumaresan Natesan International Journal of Recent Technology and Engineering (IJRTE) 8 (4 …, 2019 | 6* | 2019 |
| CMOS implementation and performance analysis of known approximate 4: 2 compressors P Anguraj, T Krishnan, S Subramanian Journal of Electronic Testing 38 (4), 353-370, 2022 | 5 | 2022 |
| Area-efficient dual-mode fused floating-point three-term adder K Thiruvenkadam, J Ramesh, AS Pillai Circuits, Systems, and Signal Processing 38, 173-190, 2019 | 5 | 2019 |
| Design and implementation of area efficient EAIC modulo adder T Krishnan, S Saravanan, P Anguraj, AS Pillai Materials Today: Proceedings 33, 3751-3756, 2020 | 4 | 2020 |
| An area efficient multi-mode quadruple precision floating point adder K Thiruvenkadam, J Ramesh, V Kalaiyarasi Microprocessors and Microsystems 45, 310-323, 2016 | 4 | 2016 |
| Design and Analysis of Improved Low Power and High-Speed N-Bit Adder MK Roberts, P Anguraj, T Krishnan 2021 International Conference on Decision Aid Sciences and Application (DASA …, 2021 | 3 | 2021 |
| Design and realization of area-efficient approximate multiplier structures for image processing applications P Anguraj, T Krishnan Microprocessors and Microsystems 102, 104925, 2023 | 2 | 2023 |
| VLSI implementation of high speed multiplier architecture using VHBCSE algorithm for DSP applications VK Perumal, R Jayabalan, T Krishnan Analog Integrated Circuits and Signal Processing 113 (3), 307-313, 2022 | 2 | 2022 |
| Design of area-efficient modified decoder-based imprecise multiplier for error-resilient applications P Anguraj, T Krishnan Microelectronics Journal 141, 105957, 2023 | 1 | 2023 |
| Design of area efficient unified binary/decimal adder/subtractor using triple carry based prefix adder T Krishnan, P Anguraj, S Saravanan, A Vidya, K Sivanandam 2022 8th International Conference on Advanced Computing and Communication …, 2022 | 1 | 2022 |
| Developing and Assessinginexact Multiplierarchitectures for Imageprocessing P Anguraj, T Krishnan | | 2024 |
| Protection of FPGA IP core using lock and unlock mechanism VK Perumal, S Sundaralingam, MN Jafarali, T Krishnan AIP Conference Proceedings 2640 (1), 2022 | | 2022 |
| Detection of Leukemia and Sickle Cell Anemia Using Segmentation of Microscopic Images K Thiruvenkadam, S Saravanan Biosc.Biotech.Res.Comm. 13 (April-May-June 2020), Pp-902-907, 2020 | | 2020 |
| DESIGN OF HIGH SPEED AND LOW POWER ADDER USING MODIFIED HYBRID FULL ADDER J Sandhiya, K Thiruvenkadam, J Ramesh International Journal of Applied Engineering Research (IJAER) 10 (29), pp …, 2015 | | 2015 |
| DESIGN OF HIGH SPEED AND LOW POWER MODIFIED BOOTH ADD MULTIPLY OPERATOR FOR FFT APPLICATION P Arivazhagan, K Thiruvenkadam, J Ramesh International Journal of Applied Engineering Research (IJAER) 10 (29), pp …, 2015 | | 2015 |
Parthibaraj ANGURAJAssistant Professor, Department of ECE, K. Ramakrishnan College of Technology在 krct.ac.in 的电子邮件经过验证
Parthibaraj ANGURAJAssistant Professor, Department of ECE, K. Ramakrishnan College of Technology在 krct.ac.in 的电子邮件经过验证
Ramesh JayabalanProfessor, Electronics and Communication Engineering, PSG College of Technology在 psgtech.ac.in 的电子邮件经过验证