| Exploring tunnel-FET for ultra low power analog applications: A case study on operational transconductance amplifier AR Trivedi, S Carlo, S Mukhopadhyay Proceedings of the 50th annual design automation conference, 1-6, 2013 | 117 | 2013 |
| Performance evaluation of 7-nm node negative capacitance FinFET-based SRAM T Dutta, G Pahwa, AR Trivedi, S Sinha, A Agarwal, YS Chauhan IEEE Electron Device Letters 38 (8), 1161-1164, 2017 | 94 | 2017 |
| RF SOI switch FET design and modeling tradeoffs for GSM applications S Parthasarathy, A Trivedi, S Sirohi, R Groves, M Olsen, YS Chauhan, ... 2010 23rd International Conference on VLSI Design, 194-199, 2010 | 87 | 2010 |
| Spiking neurons from tunable Gaussian heterojunction transistors ME Beck, A Shylendra, VK Sangwan, S Guo, WA Gaviria Rojas, H Yoo, ... Nature communications 11 (1), 1565, 2020 | 78 | 2020 |
| Low power restricted Boltzmann machine using mixed-mode magneto-tunneling junctions S Nasrin, JL Drobitch, S Bandyopadhyay, AR Trivedi IEEE Electron Device Letters 40 (2), 345-348, 2019 | 53 | 2019 |
| Reconfigurable MoS2 Memtransistors for Continuous Learning in Spiking Neural Networks J Yuan, SE Liu, A Shylendra, WA Gaviria Rojas, S Guo, H Bergeron, S Li, ... Nano letters 21 (15), 6432-6440, 2021 | 44 | 2021 |
| Application of silicon-germanium source tunnel-fet to enable ultralow power cellular neural network-based associative memory AR Trivedi, S Datta, S Mukhopadhyay IEEE Transactions on Electron Devices 61 (11), 3707-3715, 2014 | 42 | 2014 |
| Ultra-low power electronics with Si/Ge tunnel FET AR Trivedi, MF Amir, S Mukhopadhyay 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014 | 42 | 2014 |
| Energy-efficient acceleration of deep neural networks on realtime-constrained embedded edge devices B Kim, S Lee, AR Trivedi, WJ Song IEEE Access 8, 216259-216270, 2020 | 27 | 2020 |
| Mf-net: Compute-in-memory sram for multibit precision inference using memory-immersed data conversion and multiplication-free operators S Nasrin, D Badawi, AE Cetin, W Gomes, AR Trivedi IEEE Transactions on Circuits and Systems I: Regular Papers 68 (5), 1966-1978, 2021 | 24 | 2021 |
| Potential of ultralow-power cellular neural image processing with Si/Ge tunnel FET AR Trivedi, S Mukhopadhyay IEEE Transactions on Nanotechnology 13 (4), 627-629, 2014 | 23 | 2014 |
| MC2RAM: Markov Chain Monte Carlo Sampling in SRAM for Fast Bayesian Inference P Shukla, A Shylendra, T Tulabandhula, AR Trivedi 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 22 | 2020 |
| Bayesian reasoning machine on a magneto-tunneling junction network S Nasrin, J Drobitch, P Shukla, T Tulabandhula, S Bandyopadhyay, ... Nanotechnology 31 (48), 484001, 2020 | 22 | 2020 |
| Negative gate transconductance in gate/source overlapped heterojunction tunnel FET and application to single transistor phase encoder AR Trivedi, KZ Ahmed, S Mukhopadhyay IEEE Electron Device Letters 36 (2), 201-203, 2015 | 22 | 2015 |
| A Simulation Study of Oxygen Vacancy-Induced Variability in /Metal Gated SOI FinFET AR Trivedi, T Ando, A Singhee, P Kerber, E Acar, DJ Frank, ... IEEE Transactions on Electron Devices 61 (5), 1262-1269, 2014 | 20 | 2014 |
| Mc-cim: Compute-in-memory with monte-carlo dropouts for bayesian edge intelligence P Shukla, S Nasrin, N Darabi, W Gomes, AR Trivedi IEEE Transactions on Circuits and Systems I: Regular Papers 70 (2), 884-896, 2022 | 19 | 2022 |
| Skewed straintronic magnetotunneling-junction-based ternary content-addressable memory—Part I SD Manasi, MM Al-Rashid, J Atulasimha, S Bandyopadhyay, AR Trivedi IEEE transactions on Electron Devices 64 (7), 2835-2841, 2017 | 18 | 2017 |
| Two-dimensional materials for bio-realistic neuronal computing networks VK Sangwan, SE Liu, AR Trivedi, MC Hersam Matter 5 (12), 4133-4152, 2022 | 17 | 2022 |
| Ultralow-power localization of insect-scale drones: Interplay of probabilistic filtering and compute-in-memory P Shukla, A Muralidhar, N Iliev, T Tulabandhula, SB Fuller, AR Trivedi IEEE transactions on very large scale integration (VLSI) systems 30 (1), 68-80, 2021 | 17 | 2021 |
| Low power unsupervised anomaly detection by nonparametric modeling of sensor statistics A Shylendra, P Shukla, S Mukhopadhyay, S Bhunia, AR Trivedi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (8 …, 2020 | 17 | 2020 |
Saibal MukhopadhyayProfessor of Electrical Engineering, Georgia Institute of Technology在 ece.gatech.edu 的电子邮件经过验证
