| Plasticine: A reconfigurable architecture for parallel paterns R Prabhakar, Y Zhang, D Koeplinger, M Feldman, T Zhao, S Hadjis, ... ACM SIGARCH Computer Architecture News 45 (2), 389-402, 2017 | 320 | 2017 |
| Spatial: A language and compiler for application accelerators D Koeplinger, M Feldman, R Prabhakar, Y Zhang, S Hadjis, R Fiszel, ... Proceedings of the 39th ACM SIGPLAN Conference on Programming Language …, 2018 | 253 | 2018 |
| Automatic generation of efficient accelerators for reconfigurable hardware D Koeplinger, C Delimitrou, R Prabhakar, C Kozyrakis, Y Zhang, ... ACM SIGARCH Computer Architecture News 44 (3), 115-127, 2016 | 149 | 2016 |
| Sara: Scaling a reconfigurable dataflow accelerator Y Zhang, N Zhang, T Zhao, M Vilim, M Shahbaz, K Olukotun 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021 | 51 | 2021 |
| Capstan: A vector RDA for sparsity A Rucker, M Vilim, T Zhao, Y Zhang, R Prabhakar, K Olukotun MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021 | 32 | 2021 |
| Serving recurrent neural networks efficiently with a spatial accelerator T Zhao, Y Zhang, K Olukotun Proceedings of Machine Learning and Systems 1, 166-177, 2019 | 32 | 2019 |
| Scalable interconnects for reconfigurable spatial architectures Y Zhang, A Rucker, M Vilim, R Prabhakar, W Hwang, K Olukotun Proceedings of the 46th International Symposium on Computer Architecture …, 2019 | 31 | 2019 |
| Gorgon: Accelerating machine learning from relational data M Vilim, A Rucker, Y Zhang, S Liu, K Olukotun 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …, 2020 | 29 | 2020 |
| Plasticine: a reconfigurable accelerator for parallel patterns R Prabhakar, Y Zhang, D Koeplinger, M Feldman, T Zhao, S Hadjis, ... IEEE Micro 38 (3), 20-31, 2018 | 20 | 2018 |
| Automatic generation of efficient accelerators for reconfigurable hardware. In 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA) D Koeplinger, R Prabhakar, Y Zhang, C Delimitrou, C Kozyrakis, ... Ieee, 115ś127, 2016 | 19 | 2016 |
| Reduced precision checking to detect errors in floating point arithmetic Y Zhang, R Nathan, DJ Sorin arXiv preprint arXiv:1510.01145, 2015 | 4 | 2015 |
| Coarse-grained reconfigurable architectures R Prabhakar, Y Zhang, K Olukotun NANO-CHIPS 2030: On-Chip AI for an Efficient Data-Driven World, 227-246, 2020 | 3 | 2020 |
| Efficient multiway hash join on reconfigurable hardware R Singhal, Y Zhang, JD Ullman, R Prabhakar, K Olukotun Performance Evaluation and Benchmarking for the Era of Cloud (s) 11th TPC …, 2020 | 2 | 2020 |
| Efficient multiway hash join on reconfigurable hardware K Olukotun, R Prabhakar, R Singhal, JD Ullman, Y Zhang arXiv preprint arXiv:1905.13376, 2019 | 2 | 2019 |
| Serving recurrent neural networks efficiently with a spatial architecture T Zhao, Y Zhang, K Olukotun Proceedings of the 2019 ACM Conference on Systems and Machine Learning, 2019 | 2 | 2019 |
| Accelerating SLIDE: Exploiting Sparsity on Accelerator Architectures S Ko, A Rucker, Y Zhang, P Mure, K Olukotun 2022 IEEE International Parallel and Distributed Processing Symposium …, 2022 | 1 | 2022 |
| Scaling a Reconfigurable Dataflow Accelerator Y Zhang Stanford University, 2020 | | 2020 |
Kunle OlukotunCadence Design Systems Professor of Computer Science, Stanford University在 stanford.edu 的电子邮件经过验证
