Power estimation methodology for a high-level synthesis framework S Ahuja, DA Mathaikutty, G Singh, J Stetzer, SK Shukla, A Dingankar 2009 10th International Symposium on Quality Electronic Design, 541-546, 2009 | 43 | 2009 |
Interconnect architectural state coverage measurement methodology P Mannava, S Park, A Dingankar, CT Chou, N Mittal, RV Mahalikudi, ... US Patent App. 11/965,158, 2009 | 36 | 2009 |
Model-driven test generation for system level validation D Mathaikutty, S Ahuja, A Dingankar, S Shukla High Level Design Validation and Test Workshop, 2007. HLVDT 2007. IEEE …, 2007 | 35 | 2007 |
Method and system for providing multiple instances in a single multiple-instance object KL Barrett, AT Dingankar, TN Le US Patent 5,561,740, 1996 | 27 | 1996 |
A note on error bounds for approximation in inner product spaces A Dingankar, IW Sandberg Circuits, Systems and Signal Processing 15, 515-518, 1996 | 25 | 1996 |
Optimizing thread-to-core mapping on manycore platforms with distributed Tag Directories G Liu, T Schmidt, R Dömer, A Dingankar, D Kirkpatrick Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific …, 2015 | 22 | 2015 |
Design fault directed test generation for microprocessor validation DA Mathaikutty, SK Shukla, SV Kodakara, D Lilja, A Dingankar 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 19 | 2007 |
Towards embedded runtime system level optimization for MPSoCs: on-chip task allocation T Theocharides, MK Michael, M Polycarpou, A Dingankar Proceedings of the 19th ACM Great Lakes symposium on VLSI, 121-124, 2009 | 17 | 2009 |
Assertion-based modal power estimation S Ahuja, DA Mathaikutty, S Shukla, A Dingankar 2007 Eighth International Workshop on Microprocessor Test and Verification, 3-7, 2007 | 13 | 2007 |
The unreasonable effectiveness of neural network approximation AT Dingankar IEEE Transactions on Automatic Control 44 (11), 2043-2044, 1999 | 12 | 1999 |
The unreasonable effectiveness of neural network approximation AT Dingankar Systems, Man, and Cybernetics, 1997. Computational Cybernetics and …, 1997 | 12 | 1997 |
On applications of approximation theory to identification, control and classification AT Dingankar The University of Texas at Austin, 1995 | 12 | 1995 |
The unreasonable effectiveness of neural network approximation (SMC-1997) AT Dingankar Systems, Man, and Cybernetics, 1997. Computational Cybernetics and …, 0 | 12* | |
Network approximation of dynamical systems AT Dingankar, IW Sandberg Proceedings of the 1995 International Symposium on Nonlinear Theory and its …, 1995 | 11 | 1995 |
Model based test generation for microprocessor architecture validation SV Kodakara, DA Mathaikutty, A Dingankar, S Shukla, D Lilja 20th International Conference on VLSI Design held jointly with 6th …, 2007 | 10 | 2007 |
Hardware-enabled dynamic resource allocation for manycore systems using bidding-based system feedback T Theocharides, MK Michael, M Polycarpou, A Dingankar EURASIP Journal on Embedded Systems 2010, 1-21, 2010 | 9 | 2010 |
A novel system-level on-chip resource allocation method for manycore architectures T Theocharides, MK Michael, M Polycarpou, A Dingankar Symposium on VLSI, 2008. ISVLSI'08. IEEE Computer Society Annual, 99-104, 2008 | 7 | 2008 |
Mmv: A metamodeling based microprocessor validation environment DA Mathaikutty, SV Kodakara, A Dingankar, SK Shukla, DJ Lilja IEEE transactions on very large scale integration (VLSI) systems 16 (4), 339-352, 2008 | 6 | 2008 |
A Probabilistic Analysis For Fault Detectability of Code Coverage Metrics SV Kodakara, DA Mathaikutty, A Dingankar, S Shukla, D Lilja IEEE Micro. Test Verifi.(MTV) Work-shop, 2006 | 6 | 2006 |
MMV: Metamodeling Based Microprocessor Valiation Environment A Dingankar, DA Mathaikutty, SV Kodakara, S Shukla, D Lilja High-Level Design Validation and Test Workshop, 2006. Eleventh Annual IEEE …, 2006 | 5 | 2006 |