| Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-μm to 90-nm generation P Hazucha, T Karnik, J Maiz, S Walstra, B Bloechel, J Tschanz, G Dermer, ... Electron Devices Meeting, 2003. IEDM'03 Technical Digest. IEEE International …, 2003 | 227 | 2003 |
| Measurements and analysis of SER-tolerant latch in a 90-nm dual-V T CMOS process P Hazucha, T Karnik, S Walstra, BA Bloechel, JW Tschanz, J Maiz, ... IEEE Journal of Solid-State Circuits 39 (9), 1536-1543, 2004 | 222 | 2004 |
| Impact of CMOS process scaling and SOI on the soft error rates of logic processes S Hareland, J Maiz, M Alavi, K Mistry, S Walstra, C Dai VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on, 73-74, 2001 | 205 | 2001 |
| Tunable replica circuits and adaptive voltage-frequency techniques for dynamic voltage, temperature, and aging variation tolerance J Tschanz, K Bowman, S Walstra, M Agostinelli, T Karnik, V De 2009 Symposium on VLSI Circuits, 2009 | 202 | 2009 |
| Circuit-level modeling of soft errors in integrated circuits SV Walstra, C Dai IEEE Transactions on Device and Materials Reliability 5 (3), 358-364, 2005 | 86 | 2005 |
| Frequency and recovery effects in high-κ BTI degradation S Ramey, C Prasad, M Agostinelli, S Pae, S Walstra, S Gupta, J Hicks 2009 IEEE International Reliability Physics Symposium, 1023-1027, 2009 | 57 | 2009 |
| Thin oxide thickness extrapolation from capacitance-voltage measurements SV Walstra, CT Sah Electron Devices, IEEE Transactions on 44 (7), 1136-1142, 1997 | 55 | 1997 |
| Extension of the McNutt-Sah method for measuring thin oxide thicknesses of mos devices SV Walstra, CT Sah Solid-State Electronics 42 (4), 671-673, 1998 | 19 | 1998 |
| Managing bias-temperature instability for product reliability YH Lee, W McMahon, N Mielke, YLR Lu, S Walstra 2007 International Symposium on VLSI Technology, Systems and Applications …, 2007 | 12 | 2007 |
| Impact of cmos scaling and soi on software error rates of logic processes S Hareland, J Maiz, M Alavi, K Mistry, S Walsta, C Dai VLSI Technology Digest of Technical Papers, 2001 | 9 | 2001 |
| Neutron soft error rate measurements in a 90-nm cmos process and scaling trends in sram from 0.25-/spl mu/m to 90-nm generation, Electron Devices Meeting, 2003. IEDM 03 … P Hazucha, T Karnik, J Maiz, S Walstra, B Bloechel, J Tschanz, G Dermer, ... IEEE International, Dec, 2003 | 5 | 2003 |
| The effect of intrinsic capacitance degradation on circuit performance C Dai, SV Walstra, SW Lee 1996 Symposium on VLSI Technology. Digest of Technical Papers, 196-197, 1996 | 4 | 1996 |
| Neutron-SER modeling & simulation for 0.18 µm CMOS technology C Dai, N Hakim, S Walstra, S Hareland, J Maiz, S Yu, SW Lee SISPAD 2001, 278-283, 2001 | 3 | 2001 |
| Intel Perspectives on SER S Hareland, C Dai, S Walstra, J Maiz Topical Research Conf. On Reliability, 28, 2000 | 2 | 2000 |
| CV-based oxide-thickness extrapolation procedure for thin-oxide MOS devices SV Walstra University of Florida, 1994 | 1 | 1994 |
Keith BowmanQualcomm; Intel; Georgia Institute of Technology在 qti.qualcomm.com 的电子邮件经过验证
Keith BowmanQualcomm; Intel; Georgia Institute of Technology在 qti.qualcomm.com 的电子邮件经过验证
Chetan PrasadIntel Corporation在 intel.com 的电子邮件经过验证