| More Efficient Testing of Metal-oxide Memristor-based Memory SN Mozaffari, S Tragoudas, T Haniotakis IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 43 | 2016 |
| Statistical model for subthreshold current considering process variations SN Mozaffari, A Afzali-Kusha 2nd Asia Symposium on Quality Electronic Design (ASQED), 356-360, 2010 | 25 | 2010 |
| Low power spintronic ternary content addressable memory KP Gnawali, SN Mozaffari, S Tragoudas IEEE Transactions on Nanotechnology 17 (6), 1206-1216, 2018 | 23 | 2018 |
| A Generalized Approach to Implement Efficient CMOS-Based Threshold Logic Functions SN Mozaffari, S Tragoudas, T Haniotakis IEEE Transactions on Circuits and Systems I: Regular Papers 65 (3), 946-959, 2018 | 20 | 2018 |
| An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test SN Mozaffari, B Bhaskaran, K Narayanun, A Abdollahian, V Pagalone, ... 2019 IEEE International Test Conference (ITC), pp. 1-10, 2020 | 14 | 2020 |
| Reliability enhancements in memristive neural network architectures KP Gnawali, BR Paudel, SN Mozaffari, S Tragoudas IEEE Transactions on Nanotechnology 18, 866-878, 2019 | 14 | 2019 |
| An aging resilient neural network architecture SN Mozaffari, KP Gnawali, S Tragoudas Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale …, 2018 | 12 | 2018 |
| Fast march tests for defects in resistive memory SN Mozaffari, S Tragoudas, T Haniotakis Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale …, 2015 | 11 | 2015 |
| Low power artificial neural network architecture KP Gnawali, SN Mozaffari, S Tragoudas arXiv preprint arXiv:1904.02183, 2019 | 10 | 2019 |
| Maximizing the number of threshold logic functions using resistive memory SN Mozaffari, S Tragoudas IEEE Transactions on Nanotechnology 17 (5), 897-905, 2018 | 10 | 2018 |
| A new method to identify threshold logic functions SN Mozaffari, S Tragoudas, T Haniotakis Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 9 | 2017 |
| Reducing power, area, and delay of threshold logic gates considering non-integer weights SN Mozaffari, S Tragoudas, T Haniotakis 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 7 | 2017 |
| A new block-based SSTA method considering within-die variation SK Mehr, ARA Mehr, SN Mozaffari, A Afzali-Kusha 2nd Asia Symposium on Quality Electronic Design (ASQED), 260-263, 2010 | 4 | 2010 |
| Analytical Modeling of Parametric Yield Considering Variations in Leakage Power and Performance of Nano-Scaled Integrated Circuits H Aghababa, N Mozaffari, B Forouzandeh SIMUL 2015, The Seventh International Conference on Advances in System …, 2015 | 3 | 2015 |
| On-Die Noise Measurement During Automatic Test Equipment (ATE) Testing and In-System-Test (IST) SN Mozaffari, B Bhaskaran, S Sarangi, S Satheesh, KL Fu, N Valentine, ... 2022 IEEE 40th VLSI Test Symposium (VTS), 1-6, 2022 | | 2022 |
| Joint-PDF of timing and power of nano-scaled CMOS digital gates due to channel length variation SN Mozaffari, H Aghababa, A Afzali-Kusha 2010 IEEE International Conference of Electron Devices and Solid-State …, 2010 | | 2010 |
| Accurate Estimation of Joint Probability Density Function of Delay and Leakage for nano-CMOS Circuits H Aghababa, SN Mozaffari, A Afzali-Kusha, B Forouzandeh | | |
| Joint Probability Distribution of Timing and Power of nano-scaled CMOS Digital Gates due to Channel Length Variation SN Mozaffari, H Aghababa, A Afzali-Kusha | | |
Ali Afzali-KushaUniversity of Tehran在 ut.ac.ir 的电子邮件经过验证
Ali Afzali-KushaUniversity of Tehran在 ut.ac.ir 的电子邮件经过验证
Hossein AghababaUniversity of Tehran在 ut.ac.ir 的电子邮件经过验证