| High aspect ratio copper through-silicon-vias for 3D integration C Song, Z Wang, Q Chen, J Cai, L Liu Microelectronic Engineering 85 (10), 1952-1956, 2008 | 81 | 2008 |
| Low capacitance through-silicon-vias with uniform benzocyclobutene insulation layers Q Chen, C Huang, Z Tan, Z Wang IEEE Transactions on Components, Packaging and Manufacturing Technology 3 (5 …, 2013 | 59 | 2013 |
| Crosstalk evaluation, suppression and modeling in 3D through-strata-via (TSV) network Z Xu, A Beece, D Zhang, Q Chen, KN Chen, K Rose, JQ Lu 3D Systems Integration Conference (3DIC), 2010 IEEE International, 1-8, 2010 | 50 | 2010 |
| High aspect ratio and low capacitance through-silicon-vias (TSVs) with polymer insulation layers C Huang, Q Chen, D Wu, Z Wang Microelectronic Engineering 104, 12-17, 2013 | 39 | 2013 |
| Benzocyclobutene polymer filling of high aspect-ratio annular trenches for fabrication of Through-Silicon-Vias (TSVs) Q Chen, C Huang, Z Wang Microelectronics Reliability 52 (11), 2670-2676, 2012 | 39 | 2012 |
| Ultralow-capacitance through-silicon vias with annular air-gap insulation layers Q Chen, C Huang, D Wu, Z Tan, Z Wang IEEE Transactions on Electron Devices 60 (4), 1421-1426, 2013 | 37 | 2013 |
| Air-Gap Through-Silicon Vias C Huang, Q Chen, Z Wang IEEE electron device letters 34 (3), 441-443, 2013 | 34 | 2013 |
| Chip-to-wafer (C2W) 3D integration with well-controlled template alignment and wafer-level bonding Q Chen, D Zhang, Z Wang, L Liu, JJQ Lu 2011 IEEE 61st electronic components and technology conference (ECTC), 1-6, 2011 | 29 | 2011 |
| The influence of ultrasonic agitation on copper electroplating of blind-vias for SOI three-dimensional integration Q Chen, Z Wang, J Cai, L Liu Microelectronic Engineering 87 (3), 527-531, 2010 | 29 | 2010 |
| Characterization and modeling of solder balls and through-strata-vias (TSVs) in 3D architecture Z Xu, A Beece, D Zhang, Q Chen, K Rose, JQ Lu 19th Topical Meeting on Electrical Performance of Electronic Packaging and …, 2010 | 28 | 2010 |
| A novel chip-to-wafer (C2W) three-dimensional (3D) integration approach using a template for precise alignment Q Chen, D Zhang, Z Xu, A Beece, R Patti, Z Tan, Z Wang, L Liu, JQ Lu Microelectronic Engineering 92, 15-18, 2012 | 22 | 2012 |
| Polymer liner formation in high aspect ratio through-silicon-vias for 3-D integration C Huang, Q Chen, Z Wang IEEE Transactions on Components, Packaging and Manufacturing Technology 3 (7 …, 2013 | 19 | 2013 |
| Characterization of reactive ion etching of benzocyclobutente in SF 6/O 2 plasmas Q Chen, Z Wang, Z Tan, L Liu Microelectronic Engineering 87 (10), 1945-1950, 2010 | 19 | 2010 |
| Thick benzocyclobutene etching using high density SF6/O2 plasmas Q Chen, D Zhang, Z Tan, Z Wang, L Liu, JQ Lu Journal of Vacuum Science & Technology B 29 (1), 011019, 2011 | 17 | 2011 |
| Implementation of air-gap through-silicon-vias (TSVs) using sacrificial technology C Huang, Q Chen, D Wu, Z Wang IEEE Transactions on Components, Packaging and Manufacturing Technology 3 (8 …, 2013 | 16 | 2013 |
| Processing material evaluation and ultra-wideband modeling of through-strata-via (TSV) in 3D integrated circuits and systems Z Xu, A Beece, D Zhang, Q Chen, K Rose, JJQ Lu Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE …, 2010 | 11 | 2010 |
| Development of ultra-low capacitance through-silicon-vias (TSVs) with air-gap liner Q Chen, C Huang, Z Wang 2013 IEEE 63rd Electronic Components and Technology Conference, 1433-1438, 2013 | 4 | 2013 |
| Measurement and Simulation of thermal-induced stress in C2W 3D integration with template alignment Q Chen, D Wu, D Zhang, J Lu, Z Wang ECS Transactions 44 (1), 727-736, 2012 | 2 | 2012 |
