| A 65nm compute-in-memory 7T SRAM macro supporting 4-bit multiply and accumulate operation by employing charge sharing D Kushwaha, A Sharma, N Gupta, R Raj, A Joshi, J Mishra, R Kohli, ... 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 1556-1560, 2022 | 9 | 2022 |
| An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology D Kushwaha, A Joshi, N Gupta, A Sharma, S Miryala, RV Joshi, ... 2023 36th International Conference on VLSI Design and 2023 22nd …, 2023 | 8 | 2023 |
| An energy-efficient high CSNR XNOR and accumulation scheme for BNN D Kushwaha, A Joshi, CI Kumar, N Gupta, S Miryala, RV Joshi, ... IEEE Transactions on Circuits and Systems II: Express Briefs 69 (4), 2311-2315, 2022 | 8 | 2022 |
| A Fully Differential 4-Bit Analog Compute-In-Memory Architecture for Inference Application D Kushwaha, R Kohli, J Mishra, RV Joshi, S Dasgupta, A Bulusu 2023 IEEE 5th International Conference on Artificial Intelligence Circuits …, 2023 | 6 | 2023 |
| Multi-Bit Compute-In Memory Architecture Using a C-2C Ladder Network D Kushwaha, JK Abotula, R Kohli, J Mishra, S Dasgupta, A Bulusu IEEE Transactions on Circuits and Systems II: Express Briefs, 2023 | 4 | 2023 |
| A multibit mac scheme using switched capacitor based 3c multiplier for analog compute in-memory architecture N Gupta, A Joshi, D Kushwaha, V Menezes, R Sachan, S Dasgupta, ... 2022 29th IEEE International Conference on Electronics, Circuits and Systems …, 2022 | 3 | 2022 |
| A nano power voltage reference generator using of sub threshold MOSFETs D Kushwaha, DK Mishra 2017 International Conference on Information, Communication, Instrumentation …, 2017 | 1 | 2017 |
| A 415 nW, 0.8 V, voltage reference circuit using MOSFETs in saturation and sub-threshold regions D Kushwaha, DK Mishra 2016 11th International Conference on Industrial and Information Systems …, 2016 | 1 | 2016 |
| An Energy-Efficient SRAM-Based Charge Domain Compute In-Memory Architecture A Singla, D Kushwaha, G Aman, S Chakraborty, A Goel, A Bulusu, ... 2024 22nd IEEE Interregional NEWCAS Conference (NEWCAS), 233-237, 2024 | | 2024 |
| Variation-Aware Design Methodology for SRAM-Based Multi-Bit Analog Compute-in-Memory Architecture D Kushwaha, RV Joshi, A Bulusu, S Dasgupta 2024 22nd IEEE Interregional NEWCAS Conference (NEWCAS), 243-247, 2024 | | 2024 |
| Analysis of Possible Flight Operational Cost Savings by Automating Weather Forecast Updates D Kushwaha, SK Kottackal SAE Technical Paper, 2024 | | 2024 |
| System and method for enhancing pilot situational awareness for hybrid approach procedure sets S Sajjan, DK Kushwaha US Patent App. 18/218,255, 2024 | | 2024 |
| SRAM-Based Hybrid Analog Compute-In-memory Architecture to Enhance the Signal Margin D Kushwaha, RV Joshi, S Dasgupta, A Bulusu 2024 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2024 | | 2024 |
| An Area and Energy-Efficient SRAM Based Time-Domain Compute-In-Memory Architecture For BNN S Chakraborty, D Kushwaha, A Bulusu, S Dasgupta 2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS …, 2024 | | 2024 |
| An Energy-Efficient Time Domain Based Compute In-Memory Architecture for Binary Neural Network S Chakraborty, D Kushwaha, A Goel, A Singla, A Bulusu, S Dasgupta 2024 25th International Symposium on Quality Electronic Design (ISQED), 1-6, 2024 | | 2024 |
| SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology D Kushwaha, A Joshi, A Goel, RV Joshi, S Dasgupta, A Bulusu 2024 25th International Symposium on Quality Electronic Design (ISQED), 1-8, 2024 | | 2024 |
| Time-Domain-Based Non-volatile In-Memory Computing Architecture Using FeFETs for Binary Neural Network A Sharma, V Dixit, D Kushwaha, N Chauhan, VK Saxena, S Dasgupta, ... 2024 25th International Symposium on Quality Electronic Design (ISQED), 1-8, 2024 | | 2024 |
| An Energy-Efficient High Signal Margin Analog Compute-In-Memory Architecture D Kushwaha, R Kohli, J Mishra, J Singh, RV Joshi, S Dasgupta, A Bulusu 2024 IEEE 15th Latin America Symposium on Circuits and Systems (LASCAS), 1-5, 2024 | | 2024 |
| Scalable and symmetrical digital compute in-memory architecture US Patent App. File d, 2024 | | 2024 |
| In-memory compute core for machine learning acceleration SV Sayyaparaju, P Udupa, D Kushwaha US Patent App. 18/312,289, 2023 | | 2023 |
Bulusu AnandIndian Institute of Technology Roorkee在 ece.iitr.ac.in 的电子邮件经过验证
