| Efficient circuit clustering for area and power reduction in FPGAs A Singh, G Parthasarathy, M Marek-Sadowska ACM Transactions on Design Automation of Electronic Systems (TODAES) 7 (4 …, 2002 | 270 | 2002 |
| Interconnect resource-aware placement for hierarchical FPGAs A Singh, G Parthasarathy, M Marek-Sadowska IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE …, 2001 | 68 | 2001 |
| SATORI-a fast sequential SAT engine for circuits MK Iyer, G Parthasarathy, KT Cheng ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003 | 61 | 2003 |
| An efficient sequential SAT solver with improved search strategies F Lu, MK Iyer, G Parthasarathy, LC Wang, KT Cheng, KC Chen Design, Automation and Test in Europe, 1102-1107, 2005 | 58 | 2005 |
| An efficient finite-domain constraint solver for circuits G Parthasarathy, MK Iyer, KT Cheng, LC Wang Proceedings of the 41st annual Design Automation Conference, 212-217, 2004 | 54 | 2004 |
| Digital circuit design for minimum transient energy and a linear programming method VD Agrawal, ML Bushnell, G Parthasarathy, R Ramadoss Proceedings Twelfth International Conference on VLSI Design.(Cat. No …, 1999 | 54 | 1999 |
| Interconnect complexity-aware FPGA placement using Rent's rule G Parthasarathy, M Marek-Sadowska, A Mukherjee, A Singh Proceedings of the 2001 international workshop on System-level interconnect …, 2001 | 47 | 2001 |
| An Analysis of ATPG and SAT algorithms for Formal Verification G Parthasarathy, CY Huang, KT Cheng Sixth IEEE International High-Level Design Validation and Test Workshop, 177-182, 2001 | 39 | 2001 |
| Method and apparatus for combined stuck-at fault and partial-scanned delay-fault built-in self test ML Bushnell, G Parthasarathy US Patent 6,247,154, 2001 | 38 | 2001 |
| Safety property verification using sequential SAT and bounded model checking G Parthasarathy, MK Iyer, KT Cheng, LC Wang IEEE design & test of computers 21 (2), 132-143, 2004 | 34 | 2004 |
| Combining ATPG and symbolic simulation for efficient validation of embedded array systems G Parthasarathy, MK Iyer, T Feng, LC Wang, KT Cheng, MS Abadir Proceedings. International Test Conference, 203-212, 2002 | 20 | 2002 |
| Efficient reachability checking using sequential SAT G Parthasarathy, MK Iyer, KT Cheng, LC Wang ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE …, 2004 | 12 | 2004 |
| Efficient conflict-based learning in an RTL circuit constraint solver MK Iyer, G Parthasarathy, KT Cheng Design, Automation and Test in Europe, 666-671, 2005 | 11 | 2005 |
| X-ray diffraction studies on graphites from Dharwar craton SR Sharma, G Parthasarathy, B Kumar Geological Society of India 51 (4), 517-522, 1998 | 11 | 1998 |
| Structural search for rtl with predicate learning G Parthasarathy, MK Iyer, KT Cheng, F Brewer Proceedings of the 42nd annual Design Automation Conference, 451-456, 2005 | 8 | 2005 |
| A comparison of BDDs, BMC, and sequential SAT for model checking G Parthasarathy, MK Iyer, KT Cheng, LC Wang Eighth IEEE International High-Level Design Validation and Test Workshop …, 2003 | 8 | 2003 |
| RTL regression test selection using machine learning G Parthasarathy, A Rushdi, P Choudhary, S Nanda, M Evans, ... 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 281-287, 2022 | 7 | 2022 |
| RTL SAT simplification by boolean and interval arithmetic reasoning G Parthasarathy, MK Iyer, KT Cheng, F Brewer ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005 | 4 | 2005 |
| SATORI-an efficient sequential SAT solver for circuits M Iyer, G Parthasarathy, KT Cheng International Conference on Computer-aided Design, 2003 | 4 | 2003 |
| On the development of an ATPG based Satisfiability Checker MK Iyer, G Parthasarathy, TKT Cheng Proceedings of IEEE Microprocessor Test and Verification Workshop, 2002 | 4 | 2002 |
Kwang-Ting (Tim) ChengChair Professor of ECE and CSE, HKUST在 ust.hk 的电子邮件经过验证
