| Semiconductor device including duty cycle correction circuit G Byun US Patent 7,292,499, 2007 | 79 | 2007 |
| An energy-efficient and high-speed mobile memory I/O interface using simultaneous bi-directional dual (base+ RF)-band signaling GS Byun, Y Kim, J Kim, SW Tam, MCF Chang IEEE Journal of Solid-State Circuits 47 (1), 117-130, 2011 | 57 | 2011 |
| A 1.8-V 700-Mb/s/pin 512-Mb DDR-II SDRAM with on-die termination and off-chip driver calibration C Yoo, KH Kyung, K Lim, HC Lee, JW Chai, NW Heo, DJ Lee, CH Kim IEEE Journal of Solid-State Circuits 39 (6), 941-951, 2004 | 50 | 2004 |
| Weak antilocalization and conductance fluctuation in a single crystalline Bi nanowire J Kim, S Lee, YM Brovman, MG Kim, P Kim, W Lee Applied Physics Letters 104 (4), 2014 | 38 | 2014 |
| Analysis of noncoherent ASK modulation-based RF-interconnect for memory interface Y Kim, SW Tam, GS Byun, H Wu, L Nan, G Reinman, J Cong, MCF Chang IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2 (2 …, 2012 | 34 | 2012 |
| An 8.4Gb/s 2.5pJ/b Mobile Memory I/O Interface Using Bi-directional and Simultaneous Dual (Base+RF)-Band Signaling GS Byun IEEE International Solid State Circuits Conference (ISSCC), pp. 488-489, 2011 | 33* | 2011 |
| Reevaluating the latency claims of 3D stacked memories DW Chang, G Byun, H Kim, M Ahn, S Ryu, NS Kim, M Schulte 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 657-662, 2013 | 32 | 2013 |
| An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+ RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression Y Kim, GS Byun, A Tang, CP Jou, HH Hsieh, G Reinman, J Cong, ... 2012 IEEE International Solid-State Circuits Conference, 50-52, 2012 | 31 | 2012 |
| A wide range CMOS temperature sensor with process variation compensation for on-chip monitoring M Jalalifar, GS Byun IEEE Sensors Journal 16 (14), 5536-5542, 2016 | 24 | 2016 |
| The DIMM tree architecture: A high bandwidth and scalable memory system K Therdsteerasukdi, GS Byun, J Ir, G Reinman, J Cong, MF Chang 2011 IEEE 29th International Conference on Computer Design (ICCD), 388-395, 2011 | 24 | 2011 |
| Integrated circuit devices having corrosion resistant fuse regions and methods of fabricating the same T Cho, HJ Kang, HW Shin, GS Byun, SJ Kim US Patent 7,180,154, 2007 | 24 | 2007 |
| The comparison features of ECG signal with different sampling frequencies and filter methods for real-time measurement NT Bui, G Byun Symmetry 13 (8), 1461, 2021 | 23 | 2021 |
| Near‐threshold charge pump circuit using dual feedback loop M Jalalifar, GS Byun Electronics Letters 49 (23), 1436-1438, 2013 | 22 | 2013 |
| Differential output driver and semiconductor device having the same G Byun, I Bae US Patent 7,288,967, 2007 | 22 | 2007 |
| Semiconductor driver circuit with signal swing balance and enhanced testing G Byun, K Kim, W Kim US Patent 7,598,762, 2009 | 20 | 2009 |
| Semiconductor memory devices and a method thereof G Byun, MH Park, H Kim US Patent App. 11/509,006, 2007 | 19 | 2007 |
| A 1.4 Gb/s DLL using 2nd order charge-pump scheme with low phase/duty error for high-speed DRAM application K Kim, JB Lee, WJ Lee, BH Jeong, GH Cho, JS Lee, GS Byun, C Kim, ... 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No …, 2004 | 19 | 2004 |
| Multi-band interconnect for inter-chip and intra-chip communications MC Chang, SW Tam, G Byun, Y Kim, K Therdsteerasukdi, J Ir, G Reinman, ... US Patent 9,178,725, 2015 | 18 | 2015 |
| Delay locked loop capable of compensating for delay of internal clock signal by variation of driving strength of output driver in semiconductor memory device G Byun, N Heo US Patent 7,068,084, 2006 | 17 | 2006 |
| A low-power 4-PAM transceiver using a dual-sampling technique for heterogeneous latency-sensitive network-on-chip GS Byun, MM Navidi IEEE Transactions on Circuits and Systems II: Express Briefs 62 (6), 613-617, 2015 | 16 | 2015 |
