| Two-dimensional modeling of the underlap graded-channel FinFET A Chattopadhyay, A Kundu, CK Sarkar, C Bose Journal of Computational Electronics 19, 688-699, 2020 | 11 | 2020 |
| Analytical modeling of sensitivity parameters influenced by practically feasible arrangement of bio-molecules in dielectric modulated FET biosensor R Das, A Chattopadhyay, M Chanda, CK Sarkar, C Bose Silicon 14 (15), 9417-9430, 2022 | 9 | 2022 |
| Analytical modeling of linearity and intermodulation distortion of 3D gate all around junctionless (GAA-JL) FET A Chattopadhyay, M Chanda, C Bose, CK Sarkar Superlattices and Microstructures 150, 106788, 2021 | 8 | 2021 |
| A linearity based comparison between symmetric and asymmetric lateral diffusion for a 22 nm Underlapped DG-MOSFET A Chattopadhyay, R Das, A Dasgupta, A Kundu, CK Sarkar Superlattices and Microstructures 107, 69-82, 2017 | 7 | 2017 |
| Effect of spacer dielectric engineering on asymmetric source underlapped double gate MOSFET using gate stack A Chattopadhyay, A Dasgupta, R Das, A Kundu, CK Sarkar Superlattices and Microstructures 101, 87-95, 2017 | 7 | 2017 |
| Influence on the analog/RF performance in graded channel Gate Stack DG-MOSFETs A Chattopadhyay, A Dutta, A Kundu, CK Sarkar 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS …, 2016 | 7 | 2016 |
| Compact analytical modeling of underlap gate stack graded channel junction accumulation mode junctionless FET in subthreshold regime A Chattopadhyay, CK Sarkar, C Bose Superlattices and Microstructures 162, 107110, 2022 | 5 | 2022 |
| Compact Modeling of Graded N-Channel Independent Gate FET with Underlaps, Spacer and S/D Straggle for Low Power Application A Chattopadhyay, C Bose, CK Sarkar Silicon 13, 375-387, 2021 | 4 | 2021 |
| Effect of channel engineering on analog/RF performance of underlapped gatestack DG-MOSFET in Sub-20nm regime A Chattopadhyay, R Das, A Dasgupta, A Kundu, CK Sarkar 2017 Devices for Integrated Circuit (DevIC), 299-302, 2017 | 4 | 2017 |
| Analytical modeling of harmonic distortions in GAA Junctionless FETs for reliable low-power applications A Chattopadhyay, M Chanda, C Bose, CK Sarkar Journal of Electronic Materials 50 (8), 4606-4618, 2021 | 3 | 2021 |
| Impact of dopant variations on junctionless cylindrical nanowire FETs A Chattopadhyay, A Pathak, P Mukherjee 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), 1-4, 2020 | 3 | 2020 |
| Performance analysis of dual material junction accumulation mode tri gate junctionless SOI FET: Modeling and Simulation M Goswami, A Chattopadhyay, C Bose Silicon 14 (12), 7157-7168, 2022 | 1 | 2022 |
| Modeling of negative capacitance underlap graded-channel junction accumulation mode junctionless FET in nano-scale regime A Chattopadhyay Micro and Nanostructures 187, 207756, 2024 | | 2024 |
| Investigation of Core–Shell Junctionless Gate-Stack DG-FET in Low-Power Applications Using Charge-Based Modeling A Chattopadhyay, C Bose Journal of Electronic Materials 53 (1), 157-170, 2024 | | 2024 |
| Influence of High-k Oxide Thickness on Gate Stack DMG Junctionless SOI MOSFET M Goswami, A Chattopadhyay, C Bose 2021 Devices for Integrated Circuit (DevIC), 193-197, 2021 | | 2021 |
| Performance and Circuit Analysis of Independent Gate FinFET A Chattopadhyay, C Bose, KS Chandan Computers and Devices for Communication: Proceedings of CODEC 2019, 427-433, 2021 | | 2021 |
