| An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET H Okuhara, K Kitamori, Y Fujita, K Usami, H Amano 2015 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2015 | 24 | 2015 |
| Real chip evaluation of a low power CGRA with optimized application mapping T Kojima, N Ando, Y Matshushita, H Okuhara, NAV Doan, H Amano Proceedings of the 9th International Symposium on Highly-Efficient …, 2018 | 22 | 2018 |
| A 297mops/0.4 mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2 K Masuyama, Y Fujita, H Okuhara, H Amano 2015 International Conference on ReConFigurable Computing and FPGAs …, 2015 | 21 | 2015 |
| Variable pipeline structure for coarse grained reconfigurable array cma N Ando, K Masuyama, H Okuhara, H Amano 2016 International Conference on Field-Programmable Technology (FPT), 217-220, 2016 | 19 | 2016 |
| Body bias grain size exploration for a coarse grained reconfigurable accelerator Y Matsushita, H Okuhara, K Masuyama, Y Fujita, R Kawano, H Amano 2016 26th International Conference on Field Programmable Logic and …, 2016 | 18 | 2016 |
| Power optimization methodology for ultralow power microcontroller with silicon on thin BOX MOSFET H Okuhara, Y Fujita, K Usami, H Amano IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (4 …, 2016 | 17 | 2016 |
| 22.1 A 12.4 TOPS/W@ 136GOPS AI-IoT system-on-chip with 16 RISC-V, 2-to-8b precision-scalable DNN acceleration and 30%-boost adaptive body biasing F Conti, D Rossi, G Paulin, A Garofalo, A Di Mauro, G Rutishauer, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 21-23, 2023 | 16 | 2023 |
| Asymmetric body bias control with low-power fd-soi technologies: Modeling and power optimization H Okuhara, AB Ahmed, JM Kühn, H Amano IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (7 …, 2018 | 15 | 2018 |
| Digitally assisted on-chip body bias tuning scheme for ultra low-power VLSI systems H Okuhara, AB Ahmed, H Amano IEEE Transactions on Circuits and Systems I: Regular Papers 65 (10), 3241-3254, 2018 | 14 | 2018 |
| Flexible software-defined packet processing using low-area hardware H Zolfaghari, D Rossi, W Cerroni, H Okuhara, C Raffaelli, J Nurmi IEEE Access 8, 98929-98945, 2020 | 11 | 2020 |
| Body bias optimization for variable pipelined CGRA T Kojima, N Ando, H Okuhara, NAV Doan, H Amano 2017 27th International Conference on Field Programmable Logic and …, 2017 | 10 | 2017 |
| Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2–8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing F Conti, G Paulin, A Garofalo, D Rossi, A Di Mauro, G Rutishauser, ... IEEE Journal of Solid-State Circuits, 2023 | 9 | 2023 |
| Glitch-aware variable pipeline optimization for CGRAs T Kojima, N Ando, H Okuhara, H Amano 2017 International Conference on ReConFigurable Computing and FPGAs …, 2017 | 8 | 2017 |
| MuCCRA4-BB: A fine-grained body biasing capable DRP JM Kühn, AB Ahmed, H Okuhara, H Amano, O Bringmann, W Rosenstiel 2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX), 1-3, 2016 | 6 | 2016 |
| Analysis of Body Bias Control for Real Time Systems CCC Torres, H Okuhara, AB Ahmed, N Yamasaki, H Amano Workshop on Synthesis And System Integration of Mixed Information …, 2016 | 5 | 2016 |
| A shared memory chip for twin-tower of chips S Terashima, T Kojima, H Okuhara, Y Matsushita, N Ando, M Namiki, ... IEICE Technical Report; IEICE Tech. Rep. 117 (273), 43-48, 2017 | 4 | 2017 |
| Time Analysis of Applying Back Gate Bias for Reconfigurable Architectures with SOTB MOSFET H Okuhara, H Amano Proceedings of The 19th Workshop on synthesis And System Integration of …, 2015 | 4 | 2015 |
| An energy-efficient low-voltage swing transceiver for mW-range IoT end-nodes H Okuhara, A Elnaqib, D Rossi, A Di Mauro, P Mayer, P Palestri, L Benini 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 3 | 2020 |
| 7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2 K Masuyama, Y Fujita, H Okuhara, H Amano 2015 25th International Conference on Field Programmable Logic and …, 2015 | 3 | 2015 |
| A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS H Okuhara, A Elnaqib, M Dazzi, P Palestri, S Benatti, L Benini, D Rossi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (10 …, 2021 | 2 | 2021 |
Hideharu AmanoKeio University在 am.ics.keio.ac.jp 的电子邮件经过验证
