Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures H Zhang, L Bauer, MA Kochte, E Schneider, C Braun, ME Imhof, ... 2013 IEEE International Test Conference (ITC), 1-10, 2013 | 53 | 2013 |
Test strategies for reliable runtime reconfigurable architectures L Bauer, C Braun, ME Imhof, MA Kochte, E Schneider, H Zhang, J Henkel, ... IEEE Transactions on Computers 62 (8), 1494-1507, 2013 | 37 | 2013 |
Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures H Zhang, L Bauer, MA Kochte, E Schneider, HJ Wunderlich, J Henkel IEEE Transactions on Computers 66 (6), 957-970, 2017 | 35 | 2017 |
GPU-Accelerated Simulation of Small Delay Faults E Schneider, MA Kochte, S Holst, X Wen, HJ Wunderlich IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 34 | 2017 |
STRAP: Stress-aware placement for aging mitigation in runtime reconfigurable architectures H Zhang, MA Kochte, E Schneider, L Bauer, HJ Wunderlich, J Henkel Proceedings of the IEEE/ACM International Conference on Computer-Aided …, 2015 | 33 | 2015 |
GPU-accelerated small delay fault simulation E Schneider, S Holst, MA Kochte, X Wen, HJ Wunderlich Proceedings of the 2015 Design, Automation & Test in Europe Conference …, 2015 | 26 | 2015 |
Scan test power simulation on GPGPUs S Holst, E Schneider, HJ Wunderlich 2012 IEEE 21st Asian Test Symposium, 155-160, 2012 | 21 | 2012 |
Optimized selection of frequencies for faster-than-at-speed test M Kampmann, MA Kochte, E Schneider, T Indlekofer, S Hellebrand, ... 2015 IEEE 24th Asian Test Symposium (ATS), 109-114, 2015 | 19 | 2015 |
Variation-aware deterministic ATPG M Sauer, I Polian, ME Imhof, A Mumtaz, E Schneider, A Czutro, ... 2014 19th IEEE European Test Symposium (ETS), 1-6, 2014 | 19 | 2014 |
Extending Aging Monitors for Early Life and Wear-Out Failure Prevention C Liu, E Schneider, M Kampmann, S Hellebrand, HJ Wunderlich 2018 IEEE 27th Asian Test Symposium (ATS), 92-97, 2018 | 17 | 2018 |
Built-in Test for Hidden Delay Faults M Kampmann, MA Kochte, C Liu, E Schneider, S Hellebrand, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 13 | 2018 |
Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses S Holst, E Schneider, MA Kochte, X Wen, HJ Wunderlich 2019 IEEE International Test Conference (ITC), 1-10, 2019 | 10 | 2019 |
Logic/clock-path-aware at-speed scan test generation for avoiding false capture failures and reducing clock stretch K Asada, X Wen, S Holst, K Miyase, S Kajihara, MA Kochte, E Schneider, ... 2015 IEEE 24th Asian Test Symposium (ATS), 103-108, 2015 | 10 | 2015 |
Data-parallel simulation for fast and accurate timing validation of CMOS circuits E Schneider, S Holst, X Wen, HJ Wunderlich Proceedings of the 2014 IEEE/ACM International Conference on Computer-Aided …, 2014 | 10 | 2014 |
Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors S Holst, E Schneider, K Kawagoe, MA Kochte, K Miyase, HJ Wunderlich, ... | 8 | 2017 |
SWIFT: Switch-Level Fault Simulation on GPUs E Schneider, HJ Wunderlich IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 7 | 2019 |
Multi-level timing simulation on GPUs E Schneider, MA Kochte, HJ Wunderlich Proceedings of the 23rd Asia and South Pacific Design Automation Conference …, 2018 | 7 | 2018 |
High-Throughput Transistor-Level Fault Simulation on GPUs E Schneider, HJ Wunderlich 2016 IEEE 25th Asian Test Symposium (ATS), 150-155, 2016 | 7 | 2016 |
Using Programmable Delay Monitors for Wear-Out and Early Life Failure Prediction C Liu, E Schneider, HJ Wunderlich 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 804-809, 2020 | 5 | 2020 |
Timing-Accurate Estimation of IR-Drop Impact on Logic-and Clock-Paths During At-Speed Scan Test S Holst, E Schneider, X Wen, S Kajihara, Y Yamato, HJ Wunderlich, ... 2016 IEEE 25th Asian Test Symposium (ATS), 19-24, 2016 | 5 | 2016 |