| A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology H Maejima, K Kanda, S Fujimura, T Takagiwa, S Ozawa, J Sato, Y Shindo, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 336-338, 2018 | 72 | 2018 |
| A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 μs and tR = 4 μs T Kouchi, M Kakoi, N Kumazaki, A Sugahara, A Imamoto, Y Kajiyama, ... IEEE Journal of Solid-State Circuits 56 (1), 225-234, 2020 | 22 | 2020 |
| 13.5 A 128Gb 1b/Cell 96-Word-Line-Layer 3D Flash Memory to Improve Random Read Latency with tPROG=75µs and tR=4µs T Kouchi, N Kumazaki, M Yamaoka, S Bushnaq, T Kodama, Y Ishizaki, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 226-228, 2020 | 22* | 2020 |
| Semiconductor memory device and memory system, read order S Bushnaq, T Akamine, M Shirakawa US Patent 9,767,910, 2017 | 21 | 2017 |
| Semiconductor memory device, double side decoding S Bushnaq, M Shirakawa US Patent 9,773,555, 2017 | 15 | 2017 |
| Semiconductor memory device, tunable vpass param S Bushnaq, M Shirakawa, H Shiga US Patent 9,767,908, 2017 | 11* | 2017 |
| Semiconductor memory device, tier dec S Bushnaq US Patent 10,325,656, 2019 | 10 | 2019 |
| Memory device, Quick Setup Read A Sugahara, T Handa, R Isomura, K Uehara, J Sato, N Asaoka, ... US Patent 10,957,404, 2021 | 9* | 2021 |
| All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance S Bushnaq, T Nakura, M Ikeda, K Asada 2009 12th International Symposium on Design and Diagnostics of Electronic …, 2009 | 9 | 2009 |
| Semiconductor storage device, VREAD assist S Bushnaq, T Hashimoto US Patent 10,325,667, 2019 | 7 | 2019 |
| Memory device block decoder S Bushnaq, X Li US Patent 9,786,377, 2017 | 7 | 2017 |
| inDepth: Force-based Interaction with Objects beyond A Physical Barrier T Yoshida, J Ogawa, KY Choi, S Bushnaq, K Nakagaki, H Ishii Proceedings of the Fifteenth International Conference on Tangible, Embedded …, 2021 | 6 | 2021 |
| Level shifter S Bushnaq, M Sato US Patent 9,953,715, 2018 | 6 | 2018 |
| Semiconductor memory device, OPDEC architecture B Sanad, N Kumazaki, Y Shibazaki US Patent 10,896,735, 2021 | 5 | 2021 |
| Semiconductor memory device, TIer Dec#4 S Bushnaq US Patent 10,580,494, 2020 | 3 | 2020 |
| All digital wireless transceiver using modified BPSK and 2/3 sub-sampling technique S Bushnaq, T Nakura, M Ikeda, K Asada 2009 IEEE 8th International Conference on ASIC, 469-472, 2009 | 3 | 2009 |
| Semiconductor storage device S Bushnaq, N Kumazaki, M Yamaoka US Patent 11,152,069, 2021 | 2 | 2021 |
| Range extension of inductive coupling communication using multi-stage resonance S Bushnaq, M Ikeda, K Asada 2012 International Symposium on Communications and Information Technologies …, 2012 | 2 | 2012 |
| Semiconductor storage device S Bushnaq, N Kumazaki, M Yamaoka US Patent 11,657,874, 2023 | 1 | 2023 |
| Semiconductor storage device S Bushnaq, N Kumazaki, M Yamaoka US Patent 11,915,760, 2024 | | 2024 |
