| System-level modeling of microprocessor reliability degradation due to BTI and HCI CC Chen, S Cha, T Liu, L Milor 2014 IEEE International Reliability Physics Symposium, CA. 8.1-CA. 8.9, 2014 | 34 | 2014 |
| System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown T Liu, CC Chen, S Cha, L Milor Microelectronics Reliability 55 (9-10), 1334-1340, 2015 | 26 | 2015 |
| Extraction of threshold voltage degradation modeling due to negative bias temperature instability in circuits with I/O measurements S Cha, CC Chen, T Liu, LS Milor 2014 IEEE 32nd VLSI Test Symposium (VTS), 1-6, 2014 | 18 | 2014 |
| Processor-level reliability simulator for time-dependent gate dielectric breakdown CC Chen, T Liu, S Cha, L Milor Microprocessors and Microsystems 39 (8), 950-960, 2015 | 11 | 2015 |
| System-level estimation of threshold voltage degradation due to NBTI with I/O measurements S Cha, CC Chen, LS Milor 2014 IEEE International Reliability Physics Symposium, PR. 1.1-PR. 1.7, 2014 | 10 | 2014 |
| Negative bias temperature instability and gate oxide breakdown modeling in circuits with die-to-die calibration through power supply and ground signal measurements S Cha, T Liu, L Milor IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (8 …, 2017 | 8 | 2017 |
| AVERT: An elaborate model for simulating variable retention time in DRAMs DH Kim, S Cha, LS Milor Microelectronics Reliability 55 (9-10), 1313-1319, 2015 | 8 | 2015 |
| Gate oxide breakdown parameter extraction with ground and power supply signature measurements S Cha, W Kim, L Milor Design of Circuits and Integrated Systems, 1-6, 2014 | 8 | 2014 |
| Estimation of remaining life using embedded SRAM for wearout parameter extraction W Kim, CC Chen, T Liu, S Cha, L Milor 2015 6th International Workshop on Advances in Sensors and Interfaces (IWASI …, 2015 | 7 | 2015 |
| Frontend wearout modeling from device to system with power/ground signature analysis S Cha, CC Chen, LS Milor 2014 IEEE International Integrated Reliability Workshop Final Report (IIRW …, 2014 | 7 | 2014 |
| Built-in self-test for bias temperature instability, hot-carrier injection, and gate oxide breakdown in embedded DRAMs DH Kim, S Cha, LS Milor Microelectronics Reliability 55 (9-10), 2113-2118, 2015 | 6 | 2015 |
| System-level modeling of microprocessor reliability degradation due to TDDB CC Chen, S Cha, L Milor Design of Circuits and Integrated Systems, 1-6, 2014 | 6 | 2014 |
| The die-to-die calibrated combined model of negative bias temperature instability and gate oxide breakdown from device to system S Cha, DH Kim, T Liu, LS Milor Microelectronics Reliability 55 (9-10), 1404-1411, 2015 | 5 | 2015 |
| Memory BIST for on-chip monitoring of resistive-open defects due to electromigration and stress-induced voiding in an SRAM array W Kim, S Cha, L Milor Design of Circuits and Integrated Systems, 1-6, 2014 | 5 | 2014 |
| Design for reliability: A duty-cycle management system for timing violations S Cha, DH Kim, T Liu, L Milor 2016 Conference on Design of Circuits and Integrated Systems (DCIS), 1-6, 2016 | 3 | 2016 |
| MBIST and statistical hypothesis test for time dependent dielectric breakdowns due to GOBD vs. BTDDB in an SRAM array W Kim, CC Chen, S Cha, L Milor 2015 IEEE 33rd VLSI Test Symposium (VTS), 1-6, 2015 | 2 | 2015 |
| Adaptive supply voltage and duty cycle controller for yield-power optimization of ICs S Cha, L Milor 2017 7th IEEE International Workshop on Advances in Sensors and Interfaces …, 2017 | 1 | 2017 |
| and gate oxide breakdown in embedded DRAMs DH Kim, S Cha, LS Milor | | |
