| Design and Implementation of Multistage Interconnection Networks for SoC Networks M Moazez, F Safaei, M Rezazadeh arXiv preprint arXiv:1212.0310, 2012 | 4 | 2012 |
| Multi-level execution trace based lock contention analysis M Rezazadeh, N Ezzati-Jivan, E Galea, MR Dagenais 2020 IEEE International Symposium on Software Reliability Engineering …, 2020 | 3 | 2020 |
| Comparative Performance Study of Multi-stage Interconnection Networks Using Carbon Nanotube Switches M Rezazadeh, F Safaei, MH Moaiyeri Embedded and Ubiquitous Computing (EUC), 2011 IFIP 9th International …, 2011 | 1 | 2011 |
| Performance evaluation of complex multi-thread applications through execution path analysis M Rezazadeh, N Ezzati-Jivan, SV Azhari, MR Dagenais Performance Evaluation 155, 102289, 2022 | | 2022 |
| Performance Analysis of Complex Multi-Thread Applications Through Critical Path Analysis M Rezazadeh Ecole Polytechnique, Montreal (Canada), 2019 | | 2019 |
| Flattening: An efficient approach to improving the performance of conventional MINs M Rezazadeh, F Safaei, M Moazez Microelectronics Journal 46 (10), 875-892, 2015 | | 2015 |
Farshad SafaeiAssociate Prof., Faculty of Computer Science and Engineering, Shahid Beheshti University在 sbu.ac.ir 的电子邮件经过验证
