| A “new ara” for vector computing: An open source highly efficient risc-v v 1.0 vector processor design M Perotti, M Cavalcante, N Wistoff, R Andri, L Cavigelli, L Benini 2022 IEEE 33rd International Conference on Application-specific Systems …, 2022 | 28 | 2022 |
| Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core N Wistoff, M Schneider, FK Gürkaynak, L Benini, G Heiser Fourth Workshop on RISC-V for Computer Architecture Research (CARRV), 2020 | 28 | 2020 |
| Systematic prevention of on-core timing channels by full temporal partitioning N Wistoff, M Schneider, FK Gürkaynak, G Heiser, L Benini IEEE Transactions on Computers 72 (5), 1420-1430, 2022 | 11 | 2022 |
| Microarchitectural timing channels and their prevention on an open-source 64-bit RISC-V core N Wistoff, M Schneider, FK Gürkaynak, L Benini, G Heiser 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 627-632, 2021 | 11 | 2021 |
| On-demand redundancy grouping: Selectable soft-error tolerance for a multicore cluster M Rogenmoser, N Wistoff, P Vogel, F Gürkaynak, L Benini 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 398-401, 2022 | 8 | 2022 |
| Towards a risc-v open platform for next-generation automotive ecus L Cuomo, C Scordino, A Ottaviano, N Wistoff, R Balas, L Benini, E Guidieri, ... 2023 12th Mediterranean Conference on Embedded Computing (MECO), 1-8, 2023 | 5 | 2023 |
| AutoCC: Automatic Discovery of Covert Channels in Time-Shared Hardware M Orenes-Vera, H Yun, N Wistoff, G Heiser, L Benini, D Wentzlaff, ... Proceedings of the 56th Annual IEEE/ACM International Symposium on …, 2023 | 4 | 2023 |
| Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs. L Valente, A Veeran, M Sinigaglia, Y Tortorella, A Nadalini, N Wistoff, ... HCS, 1-12, 2023 | 4 | 2023 |
| Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit … G Paulin, P Scheffler, T Benz, M Cavalcante, T Fischer, M Eggimann, ... arXiv preprint arXiv:2406.15068, 2024 | 1 | 2024 |
| A Heterogeneous RISC-V Based SoC for Secure Nano-UAV Navigation L Valente, A Nadalini, AHC Veeran, M Sinigaglia, B Sá, N Wistoff, ... IEEE Transactions on Circuits and Systems I: Regular Papers, 2024 | 1 | 2024 |
| Protego: A Low-Overhead Open-Source I/O Physical Memory Protection Unit for RISC-V N Wistoff, A Kuster, M Rogenmoser, R Balas, M Schneider, L Benini Proceedings of the 1st Safety and Security in Heterogeneous Open System-on …, 2023 | 1 | 2023 |
| Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor R Tedeschi, L Valente, G Ottavi, E Zelioli, N Wistoff, M Giacometti, ... arXiv preprint arXiv:2407.19895, 2024 | | 2024 |
| ISA Support for Hardware Resource Partitioning in RISC-V N Wistoff, R Balas, A Ottaviano, G Heiser, L Benini RISC-V Summit Europe 2024, 2024 | | 2024 |
| Proving the Absence of Microarchitectural Timing Channels S Buckley, R Sison, N Wistoff, C Millar, T Murray, G Klein, G Heiser arXiv preprint arXiv:2310.17046, 2023 | | 2023 |
| Towards Full Time Protection of an Open-Source, Out-of-Order RISC-V Core N Wistoff, G Heiser, L Benini RISC-V Summit Europe 2023, 2023 | | 2023 |
| D5. 4 Evaluation of the operating systems and hypervisors JR SYS, IMS EVI, CS EVI, LC EVI, T Cucinotta, G Ara, A Ottaviano, ... | | |
Luca BeniniETH Zürich, Università di Bologna在 unibo.it 的电子邮件经过验证
