| Plasticine: A reconfigurable architecture for parallel paterns R Prabhakar, Y Zhang, D Koeplinger, M Feldman, T Zhao, S Hadjis, ... ACM SIGARCH Computer Architecture News 45 (2), 389-402, 2017 | 304 | 2017 |
| Spatial: A language and compiler for application accelerators D Koeplinger, M Feldman, R Prabhakar, Y Zhang, S Hadjis, R Fiszel, ... Proceedings of the 39th ACM SIGPLAN Conference on Programming Language …, 2018 | 244 | 2018 |
| Automatic generation of efficient accelerators for reconfigurable hardware D Koeplinger, C Delimitrou, R Prabhakar, C Kozyrakis, Y Zhang, ... ACM SIGARCH Computer Architecture News 44 (3), 115-127, 2016 | 144 | 2016 |
| Practical design space exploration L Nardi, D Koeplinger, K Olukotun 2019 IEEE 27th International Symposium on Modeling, Analysis, and Simulation …, 2019 | 107 | 2019 |
| Generating configurable hardware from parallel patterns R Prabhakar, D Koeplinger, KJ Brown, HJ Lee, C De Sa, C Kozyrakis, ... Acm Sigplan Notices 51 (4), 651-665, 2016 | 101 | 2016 |
| Hypermapper: a practical design space exploration framework L Nardi, A Souza, D Koeplinger, K Olukotun 2019 IEEE 27th International Symposium on Modeling, Analysis, and Simulation …, 2019 | 37 | 2019 |
| Photoacoustic microscopy with a pulsed multi-color source based on stimulated Raman scattering D Koeplinger, M Liu, T Buma 2011 IEEE International Ultrasonics Symposium, 296-299, 2011 | 28 | 2011 |
| Automatic generation of efficient accelerators for reconfigurable hardware. In 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA) D Koeplinger, R Prabhakar, Y Zhang, C Delimitrou, C Kozyrakis, ... Ieee, 115ś127, 2016 | 19 | 2016 |
| Plasticine: a reconfigurable accelerator for parallel patterns R Prabhakar, Y Zhang, D Koeplinger, M Feldman, T Zhao, S Hadjis, ... IEEE Micro 38 (3), 20-31, 2018 | 17 | 2018 |
| Compiler flow logic for reconfigurable architectures DA Koeplinger, R Prabhakar, S Jairath US Patent 11,080,227, 2021 | 14 | 2021 |
| Matrix normal/transpose read and a reconfigurable data processor including same DA Koeplinger, R Prabhakar, R Sivaramakrishnan, DB Jackson, M Luttrell US Patent 10,768,899, 2020 | 5 | 2020 |
| Hardware acceleration of lucky-region fusion (LRF) algorithm for image acquisition and processing W Maignan, D Koeplinger, GW Carhart, M Aubailly, F Kiamilev, JJ Liu Photonic Applications for Aerospace, Commercial, and Harsh Environments IV …, 2013 | 5 | 2013 |
| Anti-congestion flow control for reconfigurable processors W Chen, R Prabhakar, DA Koeplinger, S Gupta, RA Chaphekar, P Ajit, ... US Patent 11,709,664, 2023 | 3 | 2023 |
| Systems and methods for memory layout determination and conflict resolution DA Koeplinger, W Chen, KJ Brown, X Gu US Patent 11,645,057, 2023 | 2 | 2023 |
| Runtime patching of configuration files GF Grohoski, MK Shah, R Prabhakar, M Luttrell, R Kumar, KH Leung, ... US Patent 11,782,729, 2023 | 1 | 2023 |
| Compiler-based input synchronization for processor with variant stage latencies W Chen, R Prabhakar, DA Koeplinger US Patent App. 18/089,157, 2023 | 1 | 2023 |
| Compile time logic for inserting a buffer between a producer operation unit and a consumer operation unit in a dataflow graph KJ Brown, DA Koeplinger, W Chen, X Gu US Patent App. 17/582,421, 2022 | 1 | 2022 |
| Compile time logic for detecting streaming compatible and broadcast compatible data access patterns KJ Brown, DA Koeplinger, W Chen, X Gu US Patent 11,237,971, 2022 | 1 | 2022 |
| Buffer Fusion and Layout Optimization NF Sheeley, R Prabhakar, DA Koeplinger US Patent App. 17/987,628, 2023 | | 2023 |
| Compile time logic for detecting and resolving memory layout conflicts DA Koeplinger, W Chen, K Brown, X Gu US Patent App. 18/136,321, 2023 | | 2023 |
Raghu PrabhakarSambaNova Systems在 sambanova.ai 的电子邮件经过验证
