Source-level execution time estimation of C programs C Brandolese, W Fornaciari, F Salice, D Sciuto Proceedings of the ninth international symposium on Hardware/software …, 2001 | 98 | 2001 |
An instruction-level functionally-based energy estimation model for 32-bits microprocessors C Brandolese, W Fornaciari, F Salice, D Sciuto Proceedings of the 37th annual design automation conference, 346-351, 2000 | 86 | 2000 |
An area estimation methodology for FPGA based designs at SystemC-level C Brandolese, W Fornaciari, F Salice Proceedings of the 41st annual Design Automation Conference, 129-132, 2004 | 82 | 2004 |
A software methodology for detecting hardware faults in VLIW data paths C Bolchini IEEE Transactions on Reliability 52 (4), 458-468, 2003 | 82 | 2003 |
Logical and physical design issues for smart card databases C Bolchini, F Salice, FA Schreiber, L Tanca ACM Transactions on Information Systems (TOIS) 21 (3), 254-285, 2003 | 70 | 2003 |
Design of VHDL-based totally self-checking finite-state machine and data-path descriptions C Bolchini, R Montandon, F Salice, D Sciuto IEEE Transactions on very large scale integration (VLSI) systems 8 (1), 98-103, 2000 | 65 | 2000 |
Integrated platform for detecting pathogenic DNA via magnetic tunneling junction-based biosensors PP Sharma, E Albisetti, M Massetti, M Scolari, C La Torre, M Monticelli, ... Sensors and Actuators B: Chemical 242, 280-287, 2017 | 61 | 2017 |
Metrics for design space exploration of heterogeneous multiprocessor embedded systems D Sciuto, F Salice, L Pomante, W Fornaciari Proceedings of the tenth international symposium on Hardware/software …, 2002 | 58 | 2002 |
LAURA—LocAlization and Ubiquitous monitoRing of pAtients for health care support A Redondi, M Tagliasacchi, M Cesana, L Borsani, P Tarrío, F Salice 2010 IEEE 21st International Symposium on Personal, Indoor and Mobile Radio …, 2010 | 56 | 2010 |
The impact of source code transformations on software power and energy consumption C Brandolese, W Fornaciari, F Salice, D Sciuto Journal of Circuits, Systems, and Computers 11 (05), 477-502, 2002 | 55 | 2002 |
Affinity-driven system design exploration for heterogeneous multiprocessor SoC C Brandolese, W Fornaciari, L Pomante, F Salice, D Sciuto IEEE transactions on computers 55 (5), 508-519, 2006 | 52 | 2006 |
Bridge: Mutual reassurance for autonomous and independent living S Mangano, H Saidinejad, F Veronese, S Comai, M Matteucci, F Salice IEEE Intelligent Systems 30 (4), 31-38, 2015 | 45 | 2015 |
Indoor human detection based on thermal array sensor data and adaptive background estimation AA Trofimova, A Masciadri, F Veronese, F Salice Journal of Computer and Communications 5 (4), 16-28, 2017 | 42 | 2017 |
Designing self-checking FPGAs through error detection codes C Bolchini, F Salice, D Sciuto 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2002 | 37 | 2002 |
Reliability properties assessment at system level: A co-design framework C Bolchini, L Pomante, F Salice, D Sciuto Proceedings Seventh International On-Line Testing Workshop, 165-171, 2001 | 36 | 2001 |
A novel methodology for designing TSC networks based on the parity bit code C Bolchini, F Salice, D Sciuto Proceedings European Design and Test Conference. ED & TC 97, 440-444, 1997 | 36 | 1997 |
A first step towards Hw/Sw partitioning of UML specifications W Fornaciari, P Micheli, F Salice, L Zampella 2003 Design, Automation and Test in Europe Conference and Exhibition, 668-673, 2003 | 33 | 2003 |
Energy estimation for 32-bit microprocessors C Brandolese, W Fornaciari, F Salice, D Sciuto Proceedings of the eighth international workshop on Hardware/software …, 2000 | 33 | 2000 |
A model of soft error effects in generic IP processors C Bolchini, A Miele, F Salice, D Sciuto 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2005 | 29 | 2005 |
Static power modeling of 32-bit microprocessors C Brandolese, F Salice, W Fornaciari, D Sciuto IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2002 | 28 | 2002 |