| Lessons and experiences with high-level synthesis S Sarkar, S Dabral, PK Tiwari, RS Mitra IEEE Design & Test of Computers 26 (4), 34-45, 2009 | 34 | 2009 |
| Directed-simulation assisted formal verification of serial protocol and bridge S Gorai, S Biswas, L Bhatia, P Tiwari, RS Mitra Proceedings of the 43rd Annual Design Automation Conference, 731-736, 2006 | 28 | 2006 |
| Using patterns for high-level modeling and specification of properties for hardware systems RS Mitra, P Tiwari, MK Saluja US Patent 7,325,209, 2008 | 24 | 2008 |
| Leveraging semi-formal and sequential equivalence techniques for multimedia SoC performance validation L Bhatia, J Gaur, P Tiwari, RS Mitra, SH Matange Proceedings of the 44th annual Design Automation Conference, 69-74, 2007 | 15 | 2007 |
| Selective Annotation Of Circuits For Efficient Formal Verification With Low Power Design Considerations VA Korthikanti, P Tiwari US Patent App. 14/596,500, 2016 | 8 | 2016 |
| System on chip I/O connectivity verification in presence of low power design considerations KM Harer, P Tiwari US Patent 9,514,267, 2016 | 5 | 2016 |
| Hybrid verification of protocol bridges P Tiwari, RS Mitra IEEE Design & Test of Computers 24 (2), 124-131, 2007 | 3 | 2007 |
| Tutorial T4B: Formal Assertion-Based Verification in Industrial Setting P Tiwari, R Mitra, M Chopra, A Jain 2007 20th International Conference on VLSI Design, 7-7, 2007 | 1 | 2007 |
| Log2NS: Enhancing Deep Learning Based Analysis of Logs With Formal to Prevent Survivorship Bias C Thimmisetty, P Tiwari, DG de la Iglesia, N Ramanan, M Sayer, ... arXiv preprint arXiv:2105.14149, 2021 | | 2021 |
| A priori formal coverage analysis for protocol properties P Tiwari, S Biswas, RS Mitra 19th International Conference on VLSI Design held jointly with 5th …, 2006 | | 2006 |
| Effective Modeling Techniques for Formal Verification of Interrupt Controllers S Biswas, D Soni, VK Mohandru, P Tiwari, RS Mitra | | |
