| The EPFL logic synthesis libraries M Soeken, H Riener, W Haaswijk, E Testa, B Schmitt, G Meuli, F Mozafari, ... arXiv preprint arXiv:1805.05121, 2022 | 123 | 2022 |
| Algebraic and Boolean optimization methods for AQFP superconducting circuits E Testa, SY Lee, H Riener, G De Micheli Proceedings of the 26th Asia and South Pacific Design Automation Conference …, 2021 | 30 | 2021 |
| A simulation-guided paradigm for logic synthesis and verification SY Lee, H Riener, A Mishchenko, RK Brayton, G De Micheli IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 26 | 2021 |
| Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis H Riener, SY Lee, A Mishchenko, G De Micheli 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 395-402, 2022 | 18 | 2022 |
| Beyond local optimality of buffer and splitter insertion for AQFP circuits SY Lee, H Riener, G De Micheli Proceedings of the 59th ACM/IEEE Design Automation Conference, 445-450, 2022 | 17 | 2022 |
| Majority-based Design Flow for AQFP Superconducting Family G Meuli, V Possani, R Singh, SY Lee, AT Calvino, DS Marakkalage, ... 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 34-39, 2022 | 12 | 2022 |
| Heuristic logic resynthesis algorithms at the core of peephole optimization SY Lee, G De Micheli IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2023 | 11 | 2023 |
| Canonicalization of threshold logic representation and its applications SY Lee, NZ Lee, JHR Jiang 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018 | 10 | 2018 |
| Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits SY Lee, H Riener, G De Micheli arXiv preprint arXiv:2109.00291, 2021 | 8 | 2021 |
| Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition SY Lee, H Riener, G De Micheli 2021 24th International Symposium on Design and Diagnostics of Electronic …, 2021 | 7 | 2021 |
| Searching Parallel Separating Hyperplanes for Effective Compression of Threshold Logic Networks SY Lee, NZ Lee, JHR Jiang 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019 | 6 | 2019 |
| Enumeration of Minimum Fanout-Free Circuit Structures SY Lee, JHR Jiang, A Mishchenko, R Brayton IWLS 2019, 2019 | 5 | 2019 |
| External Don’t Cares in Logic Synthesis SY Lee, H Riener, G De Micheli Advanced Boolean Techniques: Selected Papers from the 15th International …, 2023 | 4 | 2023 |
| Impact of Sequential Design on The Cost of Adiabatic Quantum-Flux Parametron Circuits SY Lee, CL Ayala, G De Micheli IEEE Transactions on Applied Superconductivity 33 (8), 1-9, 2023 | 2 | 2023 |
| Customizable On-the-fly Design Space Exploration for Logic Optimization of Emerging Technologies SY Lee, H Riener, G De Micheli International Logic Synthesis Workshop (IWLS), 2023 | 2 | 2023 |
| Challenges and targets of MRAM-enabled scaled spintronic logic circuits F Meng, F Ciubotaru, SY Lee, O Zografos, M Gupta, VD Nguyen, S Couet, ... arXiv 2209, 2022 | 2 | 2022 |
| An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications SY Lee, H Riener, G De Micheli arXiv preprint arXiv:2207.13487, 2022 | 2 | 2022 |
| Technology mapping for beyond-cmos circuitry with unconventional cost functions DS Marakkalage, M Walter, SY Lee, R Wille, G De Micheli 2024 IEEE 24th International Conference on Nanotechnology (NANO), 51-56, 2024 | 1 | 2024 |
| Simulation-Guided Boolean Resubstitution SY Lee, H Riener, A Mishchenko, RK Brayton, G De Micheli arXiv preprint arXiv:2007.02579, 2020 | 1 | 2020 |
| Technology Legalization and Optimization for Adiabatic Quantum-Flux Parametron SY Lee, AT Calvino, H Riener, G De Micheli IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | | 2024 |
Nian-Ze LeeLMU Munich在 sosy.ifi.lmu.de 的电子邮件经过验证
Nian-Ze LeeLMU Munich在 sosy.ifi.lmu.de 的电子邮件经过验证
Jie-Hong Roland JiangProfessor of Electrical Engineering, National Taiwan University在 ntu.edu.tw 的电子邮件经过验证