| A resource-limited hardware accelerator for convolutional neural networks in embedded vision applications S Moini, B Alizadeh, M Emad, R Ebrahimpour IEEE Transactions on Circuits and Systems II: Express Briefs 64 (10), 1217-1221, 2017 | 76 | 2017 |
| Gröbner basis based formal verification of large arithmetic circuits using gaussian elimination and cone-based polynomial extraction F Farahmandi, B Alizadeh Microprocessors and Microsystems 39 (2), 83-96, 2015 | 61 | 2015 |
| FPGA-based implementation of a real-time object recognition system using convolutional neural network AA Gilan, M Emad, B Alizadeh IEEE Transactions on Circuits and Systems II: Express Briefs 67 (4), 755-759, 2019 | 48 | 2019 |
| Modular datapath optimization and verification based on modular-HED B Alizadeh, M Fujita IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010 | 41 | 2010 |
| A formal approach for debugging arithmetic circuits O Sarbishei, M Tabandeh, B Alizadeh, M Fujita IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009 | 41 | 2009 |
| Dynamic flip-flop conversion: A time-borrowing method for performance improvement of low-power digital circuits prone to variations M Nejat, B Alizadeh, A Afzali-Kusha IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (11 …, 2014 | 31 | 2014 |
| PMTP: A MAX-SAT-based approach to detect hardware trojan using propagation of maximum transition probability A Shabani, B Alizadeh IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 25 | 2018 |
| Polynomial datapath optimization using partitioning and compensation heuristics O Sarbishei, B Alizadeh, M Fujita Proceedings of the 46th Annual Design Automation Conference, 931-936, 2009 | 24 | 2009 |
| HED: A canonical and compact hybrid word-Boolean representation as a formal model for hardware/software co-designs B Alizadeh, M Fujita International Workshop on Constraints in Formal Verification (CFV07), 15-29, 2007 | 24 | 2007 |
| Optimal operation of a virtual power plant with risk management H Taheri, A Rahimi-Kian, H Ghasemi, B Alizadeh 2012 IEEE PES Innovative Smart Grid Technologies (ISGT), 1-7, 2012 | 22 | 2012 |
| Modular-HED: A canonical decision diagram for modular equivalence verification of polynomial functions B Alizadeh, M Fujita fifth Workshop on Constraints in Formal Verification (CFV), 22-40, 2008 | 21 | 2008 |
| SAT-based integrated hardware trojan detection and localization approach through path-delay analysis M Sabri, A Shabani, B Alizadeh IEEE Transactions on Circuits and Systems II: Express Briefs 68 (8), 2850-2854, 2021 | 20 | 2021 |
| FPGA-based implementation of a novel method for estimating the Brillouin frequency shift in BOTDA and BOTDR sensors M Abbasnejad, B Alizadeh IEEE Sensors Journal 18 (5), 2015-2022, 2017 | 20 | 2017 |
| Using integer equations for high level formal verification property checking B Alizadeh, MR Kakoee Fourth International Symposium on Quality Electronic Design, 2003 …, 2003 | 20 | 2003 |
| A scalable formal debugging approach with auto-correction capability based on static slicing and dynamic ranking for RTL datapath designs B Alizadeh, P Behnam, S Sadeghi-Kohan IEEE Transactions on Computers 64 (6), 1564-1578, 2014 | 19 | 2014 |
| Guided gate-level ATPG for sequential circuits using a high-level test generation approach B Alizadeh, M Fujita 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 425-430, 2010 | 18 | 2010 |
| Formal equivalence verification and debugging techniques with auto-correction mechanism for RTL designs B Alizadeh, P Behnam Microprocessors and Microsystems 37 (8), 1108-1121, 2013 | 17 | 2013 |
| Systematic approximate logic optimization using don't care conditions S Salamat, M Ahmadi, B Alizadeh, M Fujita 2017 18th International Symposium on Quality Electronic Design (ISQED), 419-425, 2017 | 16 | 2017 |
| In-circuit mutation-based automatic correction of certain design errors using SAT mechanisms P Behnam, B Alizadeh 2015 IEEE 24th Asian Test Symposium (ATS), 199-204, 2015 | 16 | 2015 |
| Automatic merge-point detection for sequential equivalence checking of system-level and RTL descriptions B Alizadeh, M Fujita Automated Technology for Verification and Analysis: 5th International …, 2007 | 16 | 2007 |
Masahiro FujitaUniversity of Tokyo在 ee.t.u-tokyo.ac.jp 的电子邮件经过验证
