| An adaptive neuro-fuzzy model to multilevel inverter for grid connected photovoltaic system P Karuppusamy, AM Natarajan, KN Vijeyakumar Journal of Circuits, Systems and Computers 24 (05), 1550066, 2015 | 20 | 2015 |
| FPGA based implementation of MPPT algorithms for photovoltaic system under partial shading conditions A Senthilvel, KN Vijeyakumar, B Vinothkumar Microprocessors and Microsystems 77, 103011, 2020 | 19 | 2020 |
| FPGA implementation of low power high speed square root circuits KN Vijeyakumar, V Sumathy, P Vasakipriya, AD Babu 2012 IEEE International Conference on Computational Intelligence and …, 2012 | 13 | 2012 |
| VLSI implementation of high speed energy-efficient truncated multiplier KN Vijeyakumar, S Elango, S Kalaiselvi Journal of Circuits, Systems and Computers 27 (05), 1850077, 2018 | 12 | 2018 |
| Target tracking in sensor networks using energy efficient prediction based clustering algorithm VP Dayan, KN Vijeyakumar Procedia Engineering 38, 2070-2076, 2012 | 10 | 2012 |
| Design of hardware efficient high speed multiplier using modified ternary logic KN Vijeyakumar, V Sumathy, MG Devi, S Tamilselvan, RR Nair Procedia engineering 38, 2186-2195, 2012 | 8 | 2012 |
| Design of low-power high-speed error tolerant shift and add multiplier KN Vijeyakumar, V Sumathy, S Komanduri, CCG Suji Journal of computer science 7 (12), 1839, 2011 | 8 | 2011 |
| VLSI implementation of area-efficient truncated modified booth multiplier for signal processing applications KN Vijeyakumar, V Sumathy, S Elango Arabian Journal for Science and Engineering 39, 7795-7806, 2014 | 7 | 2014 |
| FPGA implementation of low power hardware efficient flagged binary coded decimal adder KN Vijeyakumar, V Sumathy, AD Babu, S Elango, S Saravanakumar International Journal of Computer Applications 46 (14), 2012 | 7 | 2012 |
| A Novel n-Decimal Reversible Radix Binary-Coded Decimal Multiplier Using Radix Encoding Scheme K Saranya, KN Vijeyakumar Circuits, Systems, and Signal Processing 40, 1743-1761, 2021 | 6 | 2021 |
| Dual space vector PWM technique for a three-phase to five-phase quasi Z-source direct matrix converter S Manivannan, N Saravanakumar, KN Vijeyakumar Automatika: časopis za automatiku, mjerenje, elektroniku, računarstvo i …, 2022 | 5 | 2022 |
| A low area FPGA implementation of reversible gate encryption with heterogeneous key generation K Saranya, KN Vijeyakumar Circuits, Systems, and Signal Processing 40, 3836-3865, 2021 | 5 | 2021 |
| VLSI implementation of high speed area efficient arithmetic unit using vedic mathematics KS K.N.Vijeyakumar, S.Kalaiselvi ICTACT journal on Microelectronics 2 (1), 198-202, 2016 | 5 | 2016 |
| Removal of high density impulse noise using morphological based adaptive unsymmetrical trimmed mid-point filter SS Dr.K.N.Vijeyakumar Journal of computer science 10 (7), 2014 | 5 | 2014 |
| Design of low power full adder using active level driving circuit KN Vijeyakumar, DRV SUMATHY, M Nithya, C Venkatnarayanan, ... WSEAS transactions on circuits and systems 18, 259-248, 2012 | 5 | 2012 |
| Three-phase power conversion using quasi Z source direct matrix converter (QZSDMC) for fixed frequency to variable frequency using direct duty ratio based pulse width … S Manivannan, N Saravanakumar, KN Vijeyakumar International Journal of Electronics 109 (7), 1184-1213, 2022 | 4 | 2022 |
| Area efficient parallel median filter using approximate comparator and faithful adder KN Vijeyakumar, PTNK Joel, SHS Jatana, N Saravanakumar, S Kalaiselvi IET Circuits, Devices & Systems 14 (8), 1318-1331, 2020 | 4 | 2020 |
| Design and performance estimation of efficient approximate carry select adder VS Nishok, P Poongodi, KN Vijeyakumar Appl. Math 12 (6), 1219-1225, 2018 | 4 | 2018 |
| An Adaptive Threshold Intensity Range Filter for Removal of Random Value Impulse Noise in Digital Images SS Dr.K.N.Vijeyakumar Journal of Theoretical and Applied Information Technology 59 (1), 2014 | 4 | 2014 |
| Three-phase to K-phase power conversion using voltage fed quasi Z source direct matrix converter with maximum constant boost control technique S Manivannan, N Saravanakumar, KN Vijeyakumar Electrical Engineering 104 (5), 3603-3617, 2022 | 2 | 2022 |
