| A CMOS dual-mode brain-computer interface chipset with 2-mV precision time-based charge balancing and stimulation-side artifact suppression H Pu, O Malekzadeh-Arasteh, AR Danesh, Z Nenadic, AH Do, P Heydari IEEE Journal of Solid-State Circuits 57 (6), 1824-1840, 2021 | 41 | 2021 |
| An energy-efficient CMOS dual-mode array architecture for high-density ECoG-based brain-machine interfaces O Malekzadeh-Arasteh, H Pu, J Lim, CY Liu, AH Do, Z Nenadic, P Heydari IEEE transactions on biomedical circuits and systems 14 (2), 332-342, 2019 | 26 | 2019 |
| Study and design of a fast start-up crystal oscillator using precise dithered injection and active inductance A Karimi-Bidhendi, H Pu, P Heydari IEEE Journal of Solid-State Circuits 54 (9), 2543-2554, 2019 | 18 | 2019 |
| Benchtop and bedside validation of a low-cost programmable cortical stimulator in a testbed for bi-directional brain-computer-interface research WJ Sohn, J Lim, PT Wang, H Pu, O Malekzadeh-Arasteh, SJ Shaw, ... Frontiers in Neuroscience 16, 1075971, 2023 | 9 | 2023 |
| Optimal artifact suppression in simultaneous electrocorticography stimulation and recording for bi-directional brain-computer interface applications H Pu, J Lim, S Kellis, CY Liu, RA Andersen, AH Do, P Heydari, Z Nenadic Journal of neural engineering 17 (2), 026038, 2020 | 8 | 2020 |
| A 40v voltage-compliance 12.75 ma maximum-current multipolar neural stimulator using time-based charge balancing technique achieving 2mv precision H Pu, AR Danesh, O Malekzadeh-Arasteh, WJ Sohn, AH Do, Z Nenadic, ... 2021 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2021 | 7 | 2021 |
| Dipole cancellation as an artifact suppression technique in simultaneous electrocorticography stimulation and recording J Lim, PT Wang, H Pu, CY Liu, S Kellis, RA Andersen, P Heydari, AH Do, ... 2019 9th International IEEE/EMBS Conference on Neural Engineering (NER), 725-729, 2019 | 7 | 2019 |
| A CMOS BD-BCI incorporating stimulation with dual-mode charge balancing and time-domain pipelined recording H Pu, AR Danesh, M Safiallah, J Lim, AH Do, Z Nenadic, P Heydari 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | 2 | 2023 |
| A fully-integrated 1µw/channel dual-mode neural data acquisition system for implantable brain-machine interfaces O Malekzadeh-Arasteh, H Pu, AR Danesh, J Lim, PT Wang, CY Liu, ... 2021 43rd Annual International Conference of the IEEE Engineering in …, 2021 | 2 | 2021 |
| A Current-Adjusting Auto-Zeroing Technique for DC-Offset and Flicker-Noise Cancellation M Safiallah, AR Danesh, H Pu, P Heydari IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023 | 1 | 2023 |
| An isolated frequency compensation technique for ultra-low-power low-noise two-stage OTAs AR Danesh, M Safiallah, H Pu, P Heydari IEEE Transactions on Circuits and Systems II: Express Briefs, 2023 | 1 | 2023 |
| A CMOS BD-BCI: Neural Recorder with Two-Step Time-Domain Quantizer and Multi-Polar Stimulator with Dual-Mode Charge Balancing AR Danesh, H Pu, M Safiallah, AH Do, Z Nenadic, P Heydari IEEE Transactions on Biomedical Circuits and Systems, 2024 | | 2024 |
| High resolution electroencephalograph signal acquisition system A Danesh, P Heydari, H Pu, Z Nenadic, AH Do, OM Arasteh US Patent App. 18/245,120, 2023 | | 2023 |
| Toward Future Brain-Computer Interface: Concurrent Neural Signal Acquisition and Brain Stimulation in CMOS H Pu University of California, Irvine, 2023 | | 2023 |
| Analog and Mixed Mode Circuits and Systems An Isolated Frequency Compensation Technique for Ultra-Low-Power Low-Noise Two-Stage OTAs......................... AR Danesh, M Safiallah, H Pu, P Heydari, K Xin, M Lai, F Lv, X Zheng, ... | | |
