| Low power reversible parallel binary adder/subtractor HG Rangaraju, U Venugopal, KN Muralidhara, KB Raja arXiv preprint arXiv:1009.6218, 2010 | 97 | 2010 |
| Design of control unit for low power AU using reversible logic HVR Aradhya, BVP Kumar, KN Muralidhara Procedia Engineering 30, 631-638, 2012 | 40 | 2012 |
| Design and optimization of reversible multiplier circuit HG Rangaraju, AB Suresh, KN Muralidhara International Journal of Computer Applications 52 (10), 2012 | 32 | 2012 |
| Design, optimization and synthesis of efficient reversible logic binary decoder RA Hv, R Chinmaye, K Muralidhara International Journal of Computers and Applications 46 (6), 2012 | 27 | 2012 |
| Design of efficient reversible binary comparator HG Rangaraju, V Hegde, KB Raja, KN Muralidhara Procedia Engineering 30, 897-904, 2012 | 25 | 2012 |
| Routing in Ad Hoc Wireless Networks using Soft Computing techniques and performance evaluation using Hypernet simulator GK Siddesh, KN Muralidhara, MN Harihar International Journal of Soft Computing and Engineering 1 (3), 91-97, 2011 | 17 | 2011 |
| Design optimization of reversible logic universal barrel shifter for low power applications R AradhyaHV, M KN International Journal of Computer Applications 40 (15), 26-34, 2012 | 15 | 2012 |
| Design of efficient reversible multiplier HG Rangaraju, AB Suresh, KN Muralidhara Advances in Computing and Information Technology: Proceedings of the Second …, 2013 | 14 | 2013 |
| Design of low power arithmetic unit based on reversible logic HV Ravish Aradhya, KN Muralidhara, BV Praveen Kumar International Journal of VLSI and Signal Processing Applications 1 (1), 30-38, 2011 | 11 | 2011 |
| PAPR reduction in OFDM systems using RCF and SLM techniques AV Manjula, KN Muralidhara International Journal of Computer Applications 158 (6), 6-9, 2017 | 8 | 2017 |
| Reduced Complexity Hybrid Ripple Carry Lookahead Adder RA HV, J Lakshmesha, KN Muralidhara International Journal of Computer Applications 70 (28), 2013 | 8 | 2013 |
| Design of efficient reversible parallel Binary adder/subtractor HG Rangaraju, U Venugopal, KN Muralidhara, KB Raja Computer Networks and Information Technologies: Second International …, 2011 | 8 | 2011 |
| Rectifying contacts on cdse films O Prakash, KN Muralidhara, K Ravindra IETE Technical Review 7 (4), 260-263, 1990 | 7 | 1990 |
| Design and optimization of n-bit reversible binary comparator HG Rangaraju, V Hegde, KB Raja, KN Muralidhara International Journal of Computer Applications 55 (18), 22-30, 2012 | 6 | 2012 |
| Design of low power reversible binary comparator HG Rangaraju, V Hegde, KB Raja, KN Muralidhara Proc. Engineering (ScienceDirect), 2011 | 6 | 2011 |
| Design of efficient reversible multiply accumulate (MAC) unit HG Rangaraju, HS Arpitha, KN Muralidhara International Journal of Computer Applications 85 (16), 2014 | 4 | 2014 |
| Hybrid Zadoff‐Chu and multilateral piecewise exponential companding transform–based PAPR reduction technique in OFDM systems AV Manjula, KNR Muralidhara International Journal of Communication Systems 33 (2), e4183, 2020 | 3 | 2020 |
| Comparative Performance Analysis of Hybrid PAPR Reduction Techniques in OFDM Systems AV Manjula, KN Muralidhara Emerging Research in Electronics, Computer Science and Technology …, 2019 | 2 | 2019 |
| Hybrid Zadoff Chu matrix transform and SLM technique for PAPR reduction in OFDM systems AV Manjula, KN Muralidhara J Electr Eng Technol 9 (6), 47-56, 2018 | 2 | 2018 |
| Design of a 5-bit, 4.87 GS/s, 240µW Flash ADC using a MUX-based decoder with Regenerative Buffer in 45-nm CMOS NB Patel, KN Muralidhara 2015 International Conference on Innovations in Information, Embedded and …, 2015 | 2 | 2015 |
