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Vemu srinivasa rao
Vemu srinivasa rao
Shri Vishnu Engineering College for Women
在 svecw.edu.in 的电子邮件经过验证
标题
引用次数
引用次数
年份
An energy efficient and high speed double tail comparator using cadence EDA tools
SR Vemu, P Mowlika, S Adinarayana
2017 International Conference on Algorithms, Methodology, Models and …, 2017
82017
An Efficient and High Speed 10 Transistor Full Adders with Lector Technique
PSSN Mowlika, VS Rao
IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-ISSN …, 0
2
Design and Implementation of an Efficient VLSI Architecture for 10T Full Adder Used in Ultra Low Power Applications
V Radha Haneesha, V Srinivasa Rao, S Adinarayana
Communication Software and Networks: Proceedings of INDIA 2019, 463-475, 2020
12020
Energy-Efficient and High-Speed Hybrid 1-Bit Full Adder
PSSN Mowlika, VS Rao
Microelectronics, Electromagnetics and Telecommunications: Proceedings of …, 2018
2018
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