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Michael A. Riepe
Michael A. Riepe
Senior Principal Engineer, Achronix Semiconductor Corp.
在 achronix.com 的电子邮件经过验证 - 首页
标题
引用次数
引用次数
年份
Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system
MA Riepe, RM Swanson, TM Burks, L Van Ginneken, KF Vahtra, H Savoj
US Patent 7,103,863, 2006
1592006
Method for generating design constraints for modules in a hierarchical integrated circuit design system
TM Burks, MA Riepe, H Savoj, RM Swanson, KE Vahtra, L Van Ginneken
US Patent 6,845,494, 2005
862005
Placement-Driven Physical-Hierarchy Generation
M Riepe, N Balasundaram, M Verbeek, H Cai, R Carpenter, J Avidan
US Patent App. 11/734,757, 2007
532007
Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis
MA Riepe, KA Sakallah
Proceedings of the 1999 international symposium on Physical design, 74-81, 1999
301999
Transistor placement for noncomplementary digital VLSI cell synthesis
MA Riepe, KA Sakallah
ACM Transactions on Design Automation of Electronic Systems (TODAES) 8 (1 …, 2003
252003
The edge-based design rule model revisited
MA Riepe, KA Sakallah
ACM Transactions on Design Automation of Electronic Systems (TODAES) 3 (3 …, 1998
131998
Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation
MA Riepe, JPM Silva, KA Sakallah, RB Brown
IEEE transactions on very large scale integration (VLSI) systems 4 (1), 113-129, 1996
121996
Delay accurate compiled-code synchronous gate-level Verilog simulation
M Riepe, K Sakallah
Proc. 2nd International Verilog HDL Conference, 121-127, 1993
31993
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