Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system MA Riepe, RM Swanson, TM Burks, L Van Ginneken, KF Vahtra, H Savoj US Patent 7,103,863, 2006 | 159 | 2006 |
Method for generating design constraints for modules in a hierarchical integrated circuit design system TM Burks, MA Riepe, H Savoj, RM Swanson, KE Vahtra, L Van Ginneken US Patent 6,845,494, 2005 | 86 | 2005 |
Placement-Driven Physical-Hierarchy Generation M Riepe, N Balasundaram, M Verbeek, H Cai, R Carpenter, J Avidan US Patent App. 11/734,757, 2007 | 53 | 2007 |
Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis MA Riepe, KA Sakallah Proceedings of the 1999 international symposium on Physical design, 74-81, 1999 | 30 | 1999 |
Transistor placement for noncomplementary digital VLSI cell synthesis MA Riepe, KA Sakallah ACM Transactions on Design Automation of Electronic Systems (TODAES) 8 (1 …, 2003 | 25 | 2003 |
The edge-based design rule model revisited MA Riepe, KA Sakallah ACM Transactions on Design Automation of Electronic Systems (TODAES) 3 (3 …, 1998 | 13 | 1998 |
Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation MA Riepe, JPM Silva, KA Sakallah, RB Brown IEEE transactions on very large scale integration (VLSI) systems 4 (1), 113-129, 1996 | 12 | 1996 |
Delay accurate compiled-code synchronous gate-level Verilog simulation M Riepe, K Sakallah Proc. 2nd International Verilog HDL Conference, 121-127, 1993 | 3 | 1993 |