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Andres Viveros Wacher
Andres Viveros Wacher
在 intel.com 的电子邮件经过验证
标题
引用次数
引用次数
年份
System margining surrogate-based optimization in post-silicon validation
FE Rangel-Patiño, JL Chávez-Hurtado, A Viveros-Wacher, ...
IEEE Transactions on Microwave Theory and Techniques 65 (9), 3109-3115, 2017
282017
Post-silicon receiver equalization metamodeling by artificial neural networks
FE Rangel-Patiño, JE Rayas-Sánchez, A Viveros-Wacher, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
242018
Analog fault identification in RF circuits using artificial neural networks and constrained parameter extraction
A Viveros-Wacher, JE Rayas-Sánchez
2018 IEEE MTT-S International Conference on Numerical Electromagnetic and …, 2018
192018
A holistic methodology for system margining and jitter tolerance optimization in post-silicon validation
FE Rangel-Patiño, A Viveros-Wacher, JE Rayas-Sánchez, ...
2016 IEEE MTT-S Latin America Microwave Conference (LAMC), 1-4, 2016
182016
A holistic formulation for system margining and jitter tolerance optimization in industrial post-silicon validation
FE Rangel-PatiÑo, A Viveros-Wacher, JE Rayas-Sánchez, ...
IEEE Transactions on Emerging Topics in Computing 8 (2), 453-463, 2017
172017
Analog gross fault identification in RF circuits using neural models and constrained parameter extraction
A Viveros-Wacher, JE Rayas-Sánchez, Z Brito-Brito
IEEE Transactions on Microwave Theory and Techniques 67 (6), 2143-2150, 2019
132019
High-speed links receiver optimization in post-silicon validation exploiting Broyden-based input space mapping
FE Rangel-Patiño, JE Rayas-Sánchez, A Viveros-Wacher, ...
2018 IEEE MTT-S International Conference on Numerical Electromagnetic and …, 2018
92018
SMV methodology enhancements for high speed I/O links of SoCs
A Viveros-Wacher, R Alejos, L Alvarez, I Diaz-Castro, B Marcial, ...
2014 IEEE 32nd VLSI Test Symposium (VTS), 1-5, 2014
82014
Eye diagram system margining surrogate-based optimization in a server silicon validation platform
F Rangel-Patino, JL Chávez-Hurtado, A Viveros-Wacher, ...
European Microw. Conf.(EuMC-2017), 540-543, 2017
72017
Eye diagram optimization based on design of experiments (DoE) to accelerate industrial testing of high speed links
A Viveros-Wacher, JE Rayas-Sánchez
2016 IEEE MTT-S Latin America Microwave Conference (LAMC), 1-3, 2016
72016
Jitter tolerance acceleration using the golden section optimization technique
A Viveros-Wacher, R Baca-Baylón, FE Rangel-Patiño, ...
2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2018
42018
Fast jitter tolerance testing for high-speed serial links in post-silicon validation
A Viveros-Wacher, R Baca-Baylón, FE Rangel-Patiño, JL Silva-Cortés, ...
IEEE Transactions on Electromagnetic Compatibility 64 (2), 516-523, 2021
22021
Industry-oriented research projects on computer-aided design of high-frequency circuits and systems at ITESO Mexico
JE Rayas-Sánchez, FE Rangel-Patiño, A Viveros-Wacher, ...
European Microw. Conf.(EuMC-2018), 588-591, 2018
22018
PCIe Gen5 physical layer equalization tuning by using K-means clustering and Gaussian process regression modeling in industrial post-silicon validation
FE Rangel-Patiño, A Viveros-Wacher, C Rajyaguru, EA Vega-Ochoa, ...
2023 IEEE MTT-S International Conference on Numerical Electromagnetic and …, 2023
12023
PCIe Gen6 Physical Layer Equalization Tuning by Using Unsupervised and Supervised Machine Learning Techniques
FE Rangel-Patiño, A Viveros-Wacher, SD Rodriguez-Saenz, ...
2023 IEEE MTT-S Latin America Microwave Conference (LAMC), 105-108, 2023
2023
High Speed Serial Links Risk Assessment in Industrial Post-Silicon Validation Exploiting Machine Learning Techniques
CA Sánchez-Martínez, P López-Meyer, E Juarez-Hernandez, ...
2020 IEEE International Test Conference (ITC), 1-5, 2020
2020
THIS ISSUE INCLUDES THE JOURNAL WITHIN A JOURNAL ON MICROWAVE SYSTEMS AND APPLICATIONS MINI-SPECIAL ISSUE ON 2016 IEEE MTT-S LATIN AMERICA MICROWAVE CONFERENCE (LAMC 2016)
PV Testa, C Carta, M Barahona, F Ellinger, EA Rojas-Nastrucci, ...
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