| A soft error tolerant 10T SRAM bit-cell with differential read capability SM Jahinuzzaman, DJ Rennie, M Sachdev IEEE Transactions on Nuclear Science 56 (6), 3768-3773, 2009 | 306 | 2009 |
| Soft error susceptibilities of 22 nm tri-gate devices N Seifert, B Gill, S Jahinuzzaman, J Basile, V Ambrose, Q Shi, R Allmon, ... IEEE Transactions on Nuclear Science 59 (6), 2666-2673, 2012 | 232 | 2012 |
| Soft error rate improvements in 14-nm technology featuring second-generation 3D tri-gate transistors N Seifert, S Jahinuzzaman, J Velamala, R Ascazubi, N Patel, B Gill, ... IEEE Transactions on Nuclear Science 62 (6), 2570-2577, 2015 | 133 | 2015 |
| An analytical model for soft error critical charge of nanometric SRAMs SM Jahinuzzaman, M Sharifkhani, M Sachdev IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (9 …, 2009 | 120 | 2009 |
| Threshold voltage instability of amorphous silicon thin-film transistors under constant current stress SM Jahinuzzaman, A Sultana, K Sakariya, P Servati, A Nathan Applied Physics Letters 87 (2), 2005 | 96 | 2005 |
| TSPC-DICE: A single phase clock high performance SEU hardened flip-flop SM Jahinuzzaman, R Islam 2010 53rd IEEE International Midwest Symposium on Circuits and Systems, 73-76, 2010 | 49 | 2010 |
| A compact hybrid current/voltage sense amplifier with offset cancellation for high-speed SRAMs M Sharifkhani, E Rahiminejad, SM Jahinuzzaman, M Sachdev IEEE transactions on very large scale integration (VLSI) systems 19 (5), 883-894, 2010 | 39 | 2010 |
| Susceptibility of planar and 3D tri-gate technologies to muon-induced single event upsets N Seifert, S Jahinuzzaman, J Velamala, N Patel 2015 IEEE International Reliability Physics Symposium, 2C. 1.1-2C. 1.6, 2015 | 33 | 2015 |
| Design and analysis of a 5.3-pJ 64-kb gated ground SRAM with multiword ECC SM Jahinuzzaman, JS Shah, DJ Rennie, M Sachdev IEEE Journal of Solid-State Circuits 44 (9), 2543-2553, 2009 | 31 | 2009 |
| Investigation of process impact on soft error susceptibility of nanometric SRAMs using a compact critical charge model SM Jahinuzzaman, M Sharifkhani, M Sachdev 9th International Symposium on Quality Electronic Design (isqed 2008), 207-212, 2008 | 27 | 2008 |
| Modeling and mitigation of soft errors in nanoscale SRAMs SM Jahinuzzaman University of Waterloo, 2008 | 14 | 2008 |
| Correlating low energy neutron SER with broad beam neutron and 200 MeV proton SER for 22nm CMOS Tri-Gate devices S Jahinuzzaman, B Gill, V Ambrose, N Seifert 2013 IEEE International Reliability Physics Symposium (IRPS), 3D. 1.1-3D. 1.6, 2013 | 13 | 2013 |
| Soft error robust flip-flops M Sachdev, SM Jahinuzzaman US Patent 7,714,628, 2010 | 13 | 2010 |
| Soft error robust impulse and TSPC flip-flops in 90nm CMOS SM Jahinuzzaman, DJ Rennie, M Sachdev 2009 2nd Microsystems and Nanoelectronics Research Conference, 45-48, 2009 | 13 | 2009 |
| A multiword based high speed ecc scheme for low-voltage embedded srams S Jahinuzzaman, T Shakir, S Lubana, JS Shah, M Sachdev ESSCIRC 2008-34th European Solid-State Circuits Conference, 226-229, 2008 | 12 | 2008 |
| A read-decoupled gated-ground SRAM architecture for low-power embedded memories W Hussain, SM Jahinuzzaman Integration 45 (3), 229-236, 2012 | 10 | 2012 |
| Dynamic data stability in low-power SRAM design M Sharifkhani, SM Jahinuzzaman, M Sachdev 2007 IEEE Custom Integrated Circuits Conference, 237-240, 2007 | 9 | 2007 |
| Dynamic data stability in SRAM cells and its implications on data stability tests M Sharifkhani, SM Jahinuzzaman, M Sachdev 2006 IEEE International Workshop on Memory Technology, Design, and Testing …, 2006 | 8 | 2006 |
| Soft error robust static random access memory cells M Sachdev, SM Jahinuzzaman US Patent 7,613,067, 2009 | 6 | 2009 |
| A scalable offset-cancelled current/voltage sense amplifier H Attarzadeh, M SharifKhani, SM Jahinuzzaman Proceedings of 2010 IEEE International Symposium on Circuits and Systems …, 2010 | 5 | 2010 |
