| An energy-efficient reconfigurable processor for binary-and ternary-weight neural networks with flexible data bit width S Yin, P Ouyang, J Yang, T Lu, X Li, L Liu, S Wei IEEE Journal of Solid-State Circuits 54 (4), 1120-1136, 2018 | 59 | 2018 |
| An ultra-high energy-efficient reconfigurable processor for deep neural networks with binary/ternary weights in 28nm CMOS S Yin, P Ouyang, J Yang, T Lu, X Li, L Liu, S Wei 2018 IEEE Symposium on VLSI Circuits, 37-38, 2018 | 37 | 2018 |
| TIMAQ: A time-domain computing-in-memory-based processor using predictable decomposed convolution for arbitrary quantized DNNs J Yang, Y Kong, Z Zhang, Z Liu, J Zhou, Y Wang, Y Liu, C Guo, T Hu, C Li, ... IEEE Journal of Solid-State Circuits 56 (10), 3021-3038, 2021 | 17 | 2021 |
| A two-stage variation-aware task mapping scheme for fault-tolerant multi-core Network-on-Chips L Zhang, J Yang, C Xue, Y Ma, S Cao 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 14 | 2017 |
| A time-domain computing-in-memory based processor using predictable decomposed convolution for arbitrary quantized DNNs J Yang, Y Kong, Z Zhang, Z Liu, J Zhou, Y Wang, Y Liu, C Guo, T Hu, C Li, ... 2020 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-4, 2020 | 5 | 2020 |
| An accurate power and temperature simulation framework for network-on-chip J Yang, S Cao 2016 International Conference on Integrated Circuits and Microsystems (ICICM …, 2016 | 4 | 2016 |
| An Energy-Efficient Architecture for Accelerating Inference of Memory-Augmented Neural Networks J Yang, L Liu, J Zhang, S Wei, S Yin 2019 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 1-6, 2019 | | 2019 |
| An analytical model for capacitance of silicon-insulator-silicon through-silicon-vias B Li, M Xiong, J Yang, Z Chen, Y Ding 2016 17th International Conference on Electronic Packaging Technology (ICEPT …, 2016 | | 2016 |
