| 16.2 A 0.19 pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS SK Mathew, SK Satpathy, MA Anders, H Kaul, SK Hsu, A Agarwal, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 262 | 2014 |
| 2.4 Gbps, 7 mW all-digital PVT-variation tolerant true random number generator for 45 nm CMOS high-performance microprocessors SK Mathew, S Srinivasan, MA Anders, H Kaul, SK Hsu, F Sheikh, ... IEEE Journal of Solid-State Circuits 47 (11), 2807-2821, 2012 | 203 | 2012 |
| A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS SK Mathew, MA Anders, B Bloechel, T Nguyen, RK Krishnamurthy, ... IEEE Journal of Solid-State Circuits 40 (1), 44-51, 2005 | 190 | 2005 |
| A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core S Mathew, M Anders, RK Krishnamurthy, S Borkar IEEE Journal of Solid-State Circuits 38 (5), 689-695, 2003 | 182 | 2003 |
| 340 mv–1.1 v, 289 gbps/w, 2090-gate nanoaes hardware accelerator with area-optimized encrypt/decrypt gf (2 4) 2 polynomials in 22 nm tri-gate cmos S Mathew, S Satpathy, V Suresh, M Anders, H Kaul, A Agarwal, S Hsu, ... IEEE Journal of Solid-State Circuits 50 (4), 1048-1058, 2015 | 162 | 2015 |
| A 320 mv 56 μw 411 gops/watt ultra-low voltage motion estimation accelerator in 65 nm cmos H Kaul, MA Anders, SK Mathew, SK Hsu, A Agarwal, RK Krishnamurthy, ... IEEE Journal of Solid-State Circuits 44 (1), 107-114, 2008 | 144 | 2008 |
| Comparison of high-performance VLSI adders in the energy-delay space VG Oklobdzija, BR Zeydel, HQ Dao, S Mathew, R Krishnamurthy IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (6), 754-758, 2005 | 144 | 2005 |
| 53 Gbps NativeComposite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors SK Mathew, F Sheikh, M Kounavis, S Gueron, A Agarwal, SK Hsu, H Kaul, ... IEEE Journal of Solid-State Circuits 46 (4), 767-776, 2011 | 137 | 2011 |
| RNG: A 300–950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS SK Mathew, D Johnston, S Satpathy, V Suresh, P Newman, MA Anders, ... IEEE Journal of Solid-State Circuits 51 (7), 1695-1704, 2016 | 127 | 2016 |
| An improved unified scalable radix-2 Montgomery multiplier D Harris, R Krishnamurthy, M Anders, S Mathew, S Hsu 17th IEEE Symposium on Computer Arithmetic (ARITH'05), 172-178, 2005 | 126 | 2005 |
| Sub-500-ps 64-b ALUs in 0.18-/spl mu/m SOI/bulk CMOS: design and scaling trends SK Mathew, RK Krishnamurthy, MA Anders, R Rios, KR Mistry, ... IEEE Journal of Solid-State Circuits 36 (11), 1636-1646, 2001 | 119 | 2001 |
| A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS SK Hsu, SK Mathew, MA Anders, BR Zeydel, VG Oklobdzija, ... IEEE Journal of solid-state circuits 41 (1), 256-264, 2005 | 118 | 2005 |
| A 4-fJ/b delay-hardened physically unclonable function circuit with selective bit destabilization in 14-nm trigate CMOS S Satpathy, SK Mathew, V Suresh, MA Anders, H Kaul, A Agarwal, ... IEEE Journal of Solid-State Circuits 52 (4), 940-949, 2017 | 111 | 2017 |
| Energy-delay estimation technique for high-performance microprocessor VLSI adders VG Oklobdzija, BR Zeydel, H Dao, S Mathew, R Krishnamurthy Proceedings 2003 16th IEEE Symposium on Computer Arithmetic, 272-279, 2003 | 98 | 2003 |
| 5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/CMOS S Vangal, MA Anders, N Borkar, E Seligman, V Govindarajulu, ... IEEE Journal of Solid-State Circuits 37 (11), 1421-1432, 2002 | 90 | 2002 |
| Variable precision floating point multiply-add circuit H Kaul, MA Anders, SK Mathew, RK Krishnamurthy, WC Hasenplaugh, ... US Patent 9,104,474, 2015 | 89 | 2015 |
| Improved power/EM side-channel attack resistance of 128-bit AES engines with random fast voltage dithering A Singh, M Kar, SK Mathew, A Rajan, V De, S Mukhopadhyay IEEE Journal of Solid-State Circuits 54 (2), 569-583, 2018 | 88 | 2018 |
| A 340 mV-to-0.9 V 20.2 Tb/s source-synchronous hybrid packet/circuit-switched 16× 16 network-on-chip in 22 nm tri-gate CMOS G Chen, MA Anders, H Kaul, SK Satpathy, SK Mathew, SK Hsu, ... IEEE Journal of Solid-State Circuits 50 (1), 59-67, 2014 | 86 | 2014 |
| An all-digital unified physically unclonable function and true random number generator featuring self-calibrating hierarchical Von Neumann extraction in 14-nm tri-gate CMOS SK Satpathy, SK Mathew, R Kumar, V Suresh, MA Anders, H Kaul, ... IEEE Journal of Solid-State Circuits 54 (4), 1074-1085, 2019 | 85 | 2019 |
| A 300 mV 494GOPS/W reconfigurable dual-supply 4-way SIMD vector processing accelerator in 45 nm CMOS H Kaul, MA Anders, SK Mathew, SK Hsu, A Agarwal, RK Krishnamurthy, ... IEEE Journal of Solid-State Circuits 45 (1), 95-102, 2009 | 76 | 2009 |
