| Sequential circuit design in quantum-dot cellular automata P Venkataramani, S Srivastava, S Bhanja 2008 8th IEEE Conference on Nanotechnology, 534-537, 2008 | 22 | 2008 |
| A test time theorem and its applications P Venkataramani, S Sindia, VD Agrawal Journal of Electronic Testing 30, 229-236, 2014 | 21 | 2014 |
| Reducing test time of power constrained test by optimal selection of supply voltage P Venkataramani, VD Agrawal 2013 26th International Conference on VLSI Design and 2013 12th …, 2013 | 21 | 2013 |
| ATE test time reduction using asynchronous clock period P Venkataramani, VD Agrawal 2013 IEEE International Test Conference (ITC), 1-10, 2013 | 18 | 2013 |
| Reducing ATE test time by voltage and frequency scaling P Venkataramani Auburn University, 2014 | 15 | 2014 |
| Finding best voltage and frequency to shorten power-constrained test time P Venkataramani, S Sindia, VD Agrawal 2013 IEEE 31st VLSI Test Symposium (VTS), 1-6, 2013 | 14 | 2013 |
| Reducing ATE time for power constrained scan test by asynchronous clocking P Venkataramani, VD Agrawal Proc. International Test Conf, 13, 2012 | 8 | 2012 |
| Test-time reduction in ATE using asynchronous clocking P Venkataramani, VD Agrawal Proc. 6th IEEE International Workshop on Design for Manufacturability and Yield, 2012 | 6 | 2012 |
| ATE Test Time Reduction by Scaling Supply Voltage and Frequency P Venkataramani, VD Agrawal Proc. 31st IEEE VLSI Test Symp, 1-3, 2014 | | 2014 |
| Reducing ATE Test Time by Scaling Voltage and Frequency P Venkataramani | | 2014 |
| ATE Test Time Reduction by Scaling Voltage and Frequency (DRAFT) P Venkataramani Auburn University, 2013 | | 2013 |
| Sequential Quantum-Dot Cellular Automata Design And Analysis Using Dynamic Bayesian Networks P Venkataramani | | 2008 |
| Test Programming for Power Constrained Devices P Venkataramani, VD Agrawal | | |
Vishwani Agrawalprofessor of electrical engineering在 eng.auburn.edu 的电子邮件经过验证
