| Memory design using a one-transistor gain cell on SOI T Ohsawa, K Fujita, T Higashi, Y Iwata, T Kajiyama, Y Asao, K Sunouchi IEEE Journal of Solid-State Circuits 37 (11), 1510-1522, 2002 | 324 | 2002 |
| Floating body RAM technology and its scalability to 32nm node and beyond T Shino, N Kusunoki, T Higashi, T Ohsawa, K Fujita, K Hatsuda, N Ikumi, ... 2006 International Electron Devices Meeting, 1-4, 2006 | 302 | 2006 |
| Semiconductor memory device T Ohsawa US Patent 6,538,916, 2003 | 275 | 2003 |
| Overview and future challenges of floating body RAM (FBRAM) technology for 32 nm technology node and beyond T Hamamoto, T Ohsawa Solid-State Electronics 53 (7), 676-683, 2009 | 270 | 2009 |
| Semiconductor memory device with floating storage bulk region and method of manufacturing the same T Ohsawa US Patent 6,621,725, 2003 | 260 | 2003 |
| Semiconductor memory device T Shino, A Nitayama, T Hamamoto, H Aochi, T Ohsawa, R Fukuda US Patent 7,609,551, 2009 | 249 | 2009 |
| Semiconductor memory device T Ohsawa US Patent 6,617,651, 2003 | 240 | 2003 |
| Semiconductor memory device and method of manufacturing the same Y Iwata, T Ohsawa, T Yamada US Patent 6,778,424, 2004 | 224 | 2004 |
| Semiconductor device S Watanabe, T Ohsawa, K Sunouchi, Y Takegawa, T Kajiyama US Patent 6,632,723, 2003 | 189 | 2003 |
| Semiconductor memory device K Fujita, T Ohsawa US Patent 6,567,330, 2003 | 182 | 2003 |
| Semiconductor memory device T Ohsawa US Patent 6,687,152, 2004 | 175 | 2004 |
| Semiconductor memory device F Horiguchi, T Ohsawa, Y Iwata, T Yamada US Patent 6,548,848, 2003 | 172 | 2003 |
| Semiconductor memory device and its manufacturing method F Horiguchi, T Ohsawa US Patent App. 09/947,908, 2002 | 153 | 2002 |
| DRAM having a power supply voltage lowering circuit T Ohsawa US Patent 6,351,426, 2002 | 142 | 2002 |
| Semiconductor integrated circuit device T Ikehashi, T Ohsawa US Patent 6,825,524, 2004 | 139 | 2004 |
| Semiconductor memory device T Ohsawa US Patent 6,650,565, 2003 | 139 | 2003 |
| DRAM having a power supply voltage lowering circuit T Ohsawa US Patent 6,292,424, 2001 | 135 | 2001 |
| Semiconductor memory device T Ikehashi, T Ohsawa, K Fujita US Patent 7,027,334, 2006 | 128 | 2006 |
| Semiconductor memory device T Ohsawa US Patent 7,457,186, 2008 | 125 | 2008 |
| Semiconductor memory device for dynamically storing data with channel body of transistor used as storage node T Yamada, F Horiguchi, T Ohsawa, Y Iwata, Y Asao US Patent 7,075,820, 2006 | 123 | 2006 |
