| A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM AS Vidhyadharan, S Vidhyadharan Microelectronics Journal 111, 105033, 2021 | 24 | 2021 |
| An efficient ultra-low-power and superior performance design of ternary half adder using CNFET and gate-overlap TFET devices S Vidhyadharan, SS Dan IEEE Transactions on Nanotechnology 20, 365-376, 2021 | 23 | 2021 |
| Suppression of ambipolar behavior and simultaneous improvement in RF performance of gate-overlap tunnel field effect transistor (GOTFET) devices R Yadav, SS Dan, S Vidhyadharan, S Hariprasad Silicon 13, 1185-1197, 2021 | 17 | 2021 |
| An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder AS Vidhyadharan, S Vidhyadharan Microelectronics Journal 107, 104961, 2021 | 16 | 2021 |
| A nanoscale gate overlap tunnel FET (GOTFET) based improved double tail dynamic comparator for ultra-low-power VLSI applications S Vidhyadharan, R Yadav, H Simhadri, SS Dan Analog Integrated Circuits and Signal Processing 101 (1), 109-117, 2019 | 15 | 2019 |
| Innovative multi-threshold gate-overlap tunnel FET (GOTFET) devices for superior ultra-low power digital, ternary and analog circuits at 45-nm technology node R Yadav, SS Dan, S Vidhyadharan, S Hariprasad Journal of Computational Electronics 19 (1), 291-303, 2020 | 13 | 2020 |
| A novel ultra-low-power gate overlap tunnel FET (GOTFET) dynamic adder S Vidhyadharan, SS Dan, R Yadav, S Hariprasad International Journal of Electronics 107 (10), 1663-1681, 2020 | 12 | 2020 |
| An advanced adiabatic logic using Gate Overlap Tunnel FET (GOTFET) devices for ultra-low power VLSI sensor applications S Vidhyadharan, R Yadav, S Hariprasad, SS Dan Analog Integrated Circuits and Signal Processing 102 (1), 111-123, 2020 | 11 | 2020 |
| Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC S Vidhyadharan, SS Dan, SV Abhay, R Yadav, S Hariprasad Integration 73, 101-113, 2020 | 8 | 2020 |
| Part II: benchmarking the performance of optimized TFET-based circuits with the standard 45 nm CMOS technology using device & circuit Co-simulation methodology S Vidhyadharan, Ramakant, G Akhilesh, V Gupta, A Ravi, SS Dan International Workshop on the Physics of Semiconductor and Devices, 619-628, 2017 | 7 | 2017 |
| High-speed and area-efficient CMOS and CNFET-based level-shifters AS Vidhyadharan, A Satheesh, K Pragnaa, S Vidhyadharan Circuits, Systems, and Signal Processing 41 (8), 4649-4670, 2022 | 6 | 2022 |
| Mux based ultra-low-power ternary adders and multiplier implemented with CNFET and 45 nm MOSFETs AS Vidhyadharan, S Vidhyadharan International Journal of Electronics 109 (1), 58-82, 2022 | 6 | 2022 |
| Memristor–CMOS hybrid ultra-low-power high-speed multivibrators AS Vidhyadharan, S Vidhyadharan Analog Integrated Circuits and Signal Processing 110 (1), 47-53, 2022 | 6 | 2022 |
| CNFET-Based Ultra-Low-Power Dual- Ternary Half Adder AS Vidhyadharan, K Bha, S Vidhyadharan Circuits, Systems, and Signal Processing 40, 4089-4105, 2021 | 6 | 2021 |
| An innovative ultra-low voltage GOTFET based regenerative-latch Schmitt trigger S Vidhyadharan, SS Dan, R Yadav, S Hariprasad Microelectronics Journal 104, 104879, 2020 | 6 | 2020 |
| An efficient design approach for implementation of 2 bit ternary flash ADC using optimized complementary TFET devices S Vidhyadharan, R Ramakant, SV Abhay, AK Shyam, MP Hirpara, ... 2019 32nd International Conference on VLSI Design and 2019 18th …, 2019 | 6 | 2019 |
| Part I: optimization of the tunnel FET device structure for achieving circuit performance better than the current standard 45 nm CMOS technology Ramakant, S Vidhyadharan, G Akhilesh, V Gupta, A Ravi, SS Dan The Physics of Semiconductor Devices: Proceedings of IWPSD 2017, 611-618, 2019 | 6 | 2019 |
| CNFET based ultra-low-power Schmitt trigger SRAM for Internet of Things (IoT) applications SV Abhay, S Vidhyadharan Wireless Personal Communications 123 (1), 357-373, 2022 | 4 | 2022 |
| Novel low and high threshold TFET based NTI and PTI cells benchmarked with standard 45 nm CMOS technology for ternary logic applications R Ramakant, S Vidhyadharan, AK Shyam, M Hirpara, T Chaudhary, ... 2019 32nd International Conference on VLSI Design and 2019 18th …, 2019 | 4 | 2019 |
| An ultra‐low‐power CNFET‐based improved Schmitt trigger design for VLSI sensor applications AS Vidhyadharan, S Vidhyadharan International Journal of Numerical Modelling: Electronic Networks, Devices …, 2021 | 2 | 2021 |
