| Design of high-speed hybrid full adders using FinFET 18nm technology A Raghunandan, DR Shilpa 2019 4th International Conference on Recent Trends on Electronics …, 2019 | 20 | 2019 |
| A wavelet technique to minimize off-chip interconnect crosstalk DR Shilpa, BV Uma 2013 International Conference on Emerging Trends in Communication, Control …, 2013 | 5 | 2013 |
| Detection of blood-related diseases using deep neural nets BK Rajithkumar, DR Shilpa, BV Uma Handbook of Research on Deep Learning Innovations and Trends, 1-15, 2019 | 2 | 2019 |
| Architectural Level Crosstalk minimization: A Tool DR Shilpa, BV Uma Procedia Computer Science 93, 117-124, 2016 | 2 | 2016 |
| Design of Adiabatic Logic Circuits using FinFET 18nm Technology A Raghunandan, DR Shilpa 2021 2nd International Conference on Communication, Computing and Industry 4 …, 2021 | 1 | 2021 |
| Verification of SerDes Design Using UVM Methodology KA Nagesh, DR Shilpa Proceeding of Fifth International Conference on Microelectronics, Computing …, 2021 | 1 | 2021 |
| Piezoelectric Energy Harvesting for Wearables DR Shilpa, A Raghunandan 2021 2nd International Conference on Communication, Computing and Industry 4 …, 2021 | | 2021 |
| Development of Low Cost System for Estimating RBC, WBC Count Using Image Processing BK Rajithkumar, DR Shilpa, BV Uma, HS Mohana International Journal of Organizational and Collective Intelligence (IJOCI …, 2021 | | 2021 |
| Design of Electrostatic Energy Harvesting Pre charge Circuit A Raghunandan, DR Shilpa 2019 International Conference on Communication and Electronics Systems …, 2019 | | 2019 |
| Novel Zero Crosstalk Encoding/decoding techniques for SOC D Majithia, P Porwal, A Krishnan, S Kumar, BV Uma, DR Shilpa 2015 IEEE International Advance Computing Conference (IACC), 968-972, 2015 | | 2015 |
| A novel area efficient encoder/decoder design for crosstalk noise elimination in SOC/ASIC V Patel, S D.R, U B.V International Journal of Scientific and Engineering Research (IJSER) 5 (5), 2014 | | 2014 |
| A Novel Design of hybrid L1 cache with soft error resilient A K, S D.R, U B.V International Journal of Embedded and Software Computing (IJESC), 2013 | | 2013 |
| VLSI partitioning using combined DT and KNN algorithm S D.R, U B.V International conference on future computing 2012, 2012 | | 2012 |
| Design of Low Power FinFET Based Adiabatic Logic Circuits in 18nm Technology A Raghunandan, DR Shilpa | | |
